Lines Matching refs:CLK_EN1
29 #define CLK_EN1 (topcrm_base + 0x10)
453 zx_gate("nandflash_ahb_hclk", "main_hclk", CLK_EN1, 0);
455 zx_gate("nandflash_wclk", "nand_wclk_mux", CLK_EN1, 1);
457 zx_gate("lsp0_apb_pclk", "main_pclk", CLK_EN1, 2);
459 zx_gate("lsp0_ahb_hclk", "main_hclk", CLK_EN1, 3);
461 zx_gate("lsp0_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 4);
463 zx_gate("lsp0_104M_wclk", "pll_lsp_104M", CLK_EN1, 5);
465 zx_gate("lsp0_16M384_wclk", "clk_16M384", CLK_EN1, 6);
467 zx_gate("lsp1_apb_pclk", "main_pclk", CLK_EN1, 7);
471 zx_gate("lsp1_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 31);
473 zx_gate("lsp1_104M_wclk", "pll_lsp_104M", CLK_EN1, 9);
475 zx_gate("lsp1_32K_clk", "clk_32K768", CLK_EN1, 10);
477 zx_gate("aon_hclk", "main_hclk", CLK_EN1, 11);
479 zx_gate("sys_ctrl_pclk", "main_pclk", CLK_EN1, 12);
481 zx_gate("dma_pclk", "main_pclk", CLK_EN1, 13);
483 zx_gate("dma_aclk", "matrix_aclk", CLK_EN1, 14);
485 zx_gate("sec_hclk", "main_hclk", CLK_EN1, 15);
487 zx_gate("aes_wclk", "sec_wclk_div", CLK_EN1, 16);
489 zx_gate("des_wclk", "sec_wclk_div", CLK_EN1, 17);
491 zx_gate("iram_aclk", "matrix_aclk", CLK_EN1, 18);
493 zx_gate("irom_aclk", "matrix_aclk", CLK_EN1, 19);
495 zx_gate("boot_ctrl_hclk", "main_hclk", CLK_EN1, 20);
497 zx_gate("efuse_clk_30", "osc", CLK_EN1, 21);