Lines Matching refs:list
26 const struct lgm_clk_branch *list)
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT)
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift,
31 list->div_width, list->div_val);
33 return clk_hw_register_fixed_rate(NULL, list->name,
34 list->parent_data[0].name,
35 list->flags, list->mux_flags);
82 const struct lgm_clk_branch *list)
84 unsigned long cflags = list->mux_flags;
86 u8 shift = list->mux_shift;
87 u8 width = list->mux_width;
90 u32 reg = list->mux_off;
98 init.name = list->name;
100 init.flags = list->flags;
101 init.parent_data = list->parent_data;
102 init.num_parents = list->num_parents;
117 lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val);
193 const struct lgm_clk_branch *list)
195 unsigned long cflags = list->div_flags;
199 u8 shift = list->div_shift;
200 u8 width = list->div_width;
201 u8 shift_gate = list->div_shift_gate;
202 u8 width_gate = list->div_width_gate;
203 u32 reg = list->div_off;
211 init.name = list->name;
213 init.flags = list->flags;
214 init.parent_data = list->parent_data;
224 div->table = list->div_table;
233 lgm_set_clk_val(div->membase, reg, shift, width, list->div_val);
240 const struct lgm_clk_branch *list)
244 hw = clk_hw_register_fixed_factor(ctx->dev, list->name,
245 list->parent_data[0].name, list->flags,
246 list->mult, list->div);
250 if (list->div_flags & CLOCK_FLAG_VAL_INIT)
251 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift,
252 list->div_width, list->div_val);
296 const struct lgm_clk_branch *list)
298 unsigned long cflags = list->gate_flags;
299 const char *pname = list->parent_data[0].name;
301 u8 shift = list->gate_shift;
304 u32 reg = list->gate_off;
312 init.name = list->name;
314 init.flags = list->flags;
330 lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val);
337 const struct lgm_clk_branch *list,
343 for (idx = 0; idx < nr_clk; idx++, list++) {
344 switch (list->type) {
346 hw = lgm_clk_register_fixed(ctx, list);
349 hw = lgm_clk_register_mux(ctx, list);
352 hw = lgm_clk_register_divider(ctx, list);
355 hw = lgm_clk_register_fixed_factor(ctx, list);
358 if (list->gate_flags & GATE_CLK_HW) {
359 hw = lgm_clk_register_gate(ctx, list);
382 list->name, list->type);
385 ctx->clk_data.hws[list->id] = hw;
535 const struct lgm_clk_ddiv_data *list,
543 for (idx = 0; idx < nr_clk; idx++, list++) {
551 init.name = list->name;
553 init.flags = list->flags;
554 init.parent_data = list->parent_data;
558 ddiv->reg = list->reg;
559 ddiv->shift0 = list->shift0;
560 ddiv->width0 = list->width0;
561 ddiv->shift1 = list->shift1;
562 ddiv->width1 = list->width1;
563 ddiv->shift_gate = list->shift_gate;
564 ddiv->width_gate = list->width_gate;
565 ddiv->shift2 = list->ex_shift;
566 ddiv->width2 = list->ex_width;
567 ddiv->flags = list->div_flags;
575 dev_err(dev, "register clk: %s failed!\n", list->name);
578 ctx->clk_data.hws[list->id] = hw;