Lines Matching defs:rate
34 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
105 * @clk: struct clk * of the DPLL to compute the rate for
107 * Compute the output rate for the OMAP4 DPLL represented by @clk.
109 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
117 unsigned long rate;
125 rate = omap2_get_dpll_rate(clk);
130 rate *= OMAP4430_REGM4XEN_MULT;
132 return rate;
136 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
137 * @clk: struct clk * of the DPLL to round a rate for
138 * @target_rate: the desired rate of the DPLL
140 * Compute the rate that would be programmed into the DPLL hardware
141 * for @clk if set_rate() were to be provided with the rate
143 * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
164 * target rate without using the 4X multiplier.
173 * 4X multiplier is equivalent to dividing the target rate by 4.
190 * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
191 * @hw: pointer to the clock to determine rate for
192 * @req: target rate request
194 * Determines which DPLL mode to use for reaching a desired rate.
196 * locked, calculates the M,N values for the DPLL via round-rate.
205 if (!req->rate)
212 if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
216 req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
221 req->best_parent_rate = req->rate;