Lines Matching refs:state
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
61 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
71 state <<= __ffs(dd->idlest_mask);
74 != state) && i < MAX_DPLL_WAIT_TRIES) {
81 clk_name, (state) ? "locked" : "bypassed");
84 clk_name, (state) ? "locked" : "bypassed", i);
134 * autoidle state across the enable, per the CDP code. If the DPLL
142 u8 state = 1;
148 state <<= __ffs(dd->idlest_mask);
152 state)
178 * Will save and restore the DPLL's autoidle state across the enable,
212 * restore the DPLL's autoidle state across the stop, per the CDP
353 * to a power saving state. Software must ensure the DPLL can not
354 * transition to a low power state while changing M/N values.
431 * to enter the target state. Intended to be used as the struct clk's
750 * Using parent clock DPLL data, look up DPLL state. If locked, set our