Lines Matching refs:clk_hw
20 struct clk_hw hw;
35 struct clk_hw hw;
213 struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
216 struct clk_hw *hw, const char *con);
223 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
233 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
257 int omap2_init_clk_clkdm(struct clk_hw *hw);
258 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
259 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
261 int omap2_dflt_clk_enable(struct clk_hw *hw);
262 void omap2_dflt_clk_disable(struct clk_hw *hw);
263 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
274 u8 omap2_init_dpll_parent(struct clk_hw *hw);
275 int omap3_noncore_dpll_enable(struct clk_hw *hw);
276 void omap3_noncore_dpll_disable(struct clk_hw *hw);
277 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
278 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
280 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
284 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
286 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
288 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
298 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
299 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
301 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
303 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
307 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
309 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
312 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,