Lines Matching defs:target_rate
125 * @target_rate: the desired DPLL rate
129 * resulting rate will not be higher than the target_rate, and that
134 * new_rate as close as possible to target_rate (but not greater than
135 * target_rate) given the current (parent_rate, n, prescaled m)
141 unsigned long target_rate,
156 if (*new_rate > target_rate) {
273 * @target_rate: desired DPLL clock rate
282 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
301 if (dd->max_rate && target_rate > dd->max_rate)
302 target_rate = dd->max_rate;
307 clk_name, target_rate);
309 scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
334 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
342 delta = target_rate - new_rate;
361 clk_name, target_rate);
367 dd->last_rounded_rate = target_rate - prev_min_delta;