Lines Matching refs:TI_CLK_MUX
39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
75 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
77 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
113 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
156 { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
220 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
221 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
316 { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
317 { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
344 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
361 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
450 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
451 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
476 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
481 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
486 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
491 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
496 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
501 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
552 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
569 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
575 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
580 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
585 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
590 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
595 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
661 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
667 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
668 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
669 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
674 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
675 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
680 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
681 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
686 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
687 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
692 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
693 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
698 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
703 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
708 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
713 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
714 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
719 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
720 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
747 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
752 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
757 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
762 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
781 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
786 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
797 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },