Lines Matching refs:TI_CLK_MUX
54 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
55 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
56 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
77 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
82 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
87 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
92 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
166 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
167 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
265 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
282 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
347 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
348 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
389 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
394 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
399 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
404 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
409 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
414 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
444 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
449 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
454 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
480 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
497 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
503 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
524 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
530 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
535 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
540 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
545 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
550 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
551 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
552 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
557 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
558 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
563 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
568 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
569 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
574 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
575 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
580 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
581 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
586 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
591 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
596 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
601 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
602 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
607 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
608 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
679 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
684 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
695 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },