Lines Matching refs:NULL
23 { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
32 NULL,
50 NULL,
54 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
55 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
56 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
73 NULL,
77 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
82 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
87 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
92 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
99 NULL,
103 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
113 { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
119 { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
124 { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
125 { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
130 { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
131 { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
132 { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
133 { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
134 { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
135 { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
136 { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
141 { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
146 { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
155 NULL,
162 NULL,
166 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
167 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
177 { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
178 { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
179 { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
180 { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
181 { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
183 { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
184 { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
186 { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
187 { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
188 { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
189 { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
190 { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
191 { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
196 { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
197 { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
203 NULL,
208 NULL,
213 NULL,
218 NULL,
223 NULL,
228 NULL,
232 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
233 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
234 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
235 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
236 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
237 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
243 { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
250 NULL,
255 NULL,
264 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
265 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
272 NULL,
281 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
282 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
289 NULL,
293 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
299 NULL,
303 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
309 NULL,
314 NULL,
318 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
319 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
320 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
325 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
326 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
327 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
334 NULL,
343 NULL,
347 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
348 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
353 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
361 { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
362 { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
367 { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
368 { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
385 NULL,
389 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
394 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
399 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
404 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
409 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
414 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
419 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
424 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
429 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
434 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
439 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
444 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
449 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
454 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
459 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
464 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
470 NULL,
479 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
480 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
487 NULL,
496 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
497 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
503 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
510 NULL,
515 NULL,
524 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
530 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
535 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
540 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
545 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
550 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
551 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
552 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
557 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
558 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
563 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
568 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
569 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
574 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
575 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
580 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
581 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
586 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
591 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
596 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
601 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
602 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
607 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
608 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
613 { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
614 { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
621 { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
627 { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
628 { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
629 { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
630 { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
631 { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
632 { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
633 { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
634 { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
635 { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
639 { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
640 { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
641 { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
642 { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
659 { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
660 { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
661 { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
662 { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" },
663 { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
667 { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
674 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
679 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
684 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
691 NULL,
695 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
700 { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
701 { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
704 { DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
705 { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
708 { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
731 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
732 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
733 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
734 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
735 DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
736 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
737 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
738 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
739 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
740 DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
741 DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
742 DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
743 DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
744 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
745 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
746 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
747 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
748 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
749 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
750 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
751 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
752 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
753 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
754 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
755 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
756 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
757 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
758 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
759 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
760 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
761 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
762 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
763 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
764 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
765 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
766 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
767 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
768 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
769 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
770 DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
771 DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
772 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
773 DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
774 DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
775 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
776 DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
777 DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
778 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
779 DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
780 DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
781 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
782 DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
783 DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
784 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
785 DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
786 DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
787 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
788 DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
789 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
790 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
791 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
792 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
793 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
794 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
795 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
796 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
797 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
798 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
799 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
800 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
801 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
802 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
803 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
804 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
805 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
806 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
807 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
808 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
809 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
810 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
811 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
812 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
813 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
814 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
815 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
816 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
817 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
818 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
819 { .node_name = NULL },