Lines Matching refs:NULL
29 { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
34 { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
40 NULL,
56 NULL,
63 NULL,
67 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
68 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
76 NULL,
80 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
81 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
89 NULL,
93 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
94 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
102 NULL,
106 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
107 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
114 NULL,
118 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
123 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
128 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
133 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
138 { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
140 { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
153 { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
158 { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
163 { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
168 { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
173 { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
174 { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
175 { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
180 { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
181 { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
182 { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
187 { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
188 { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
195 NULL,
199 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
204 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
209 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
214 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
219 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
224 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
230 NULL,
234 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
239 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
244 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
249 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
254 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
259 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
264 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
280 { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
281 { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
282 { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
283 { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
284 { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
285 { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
286 { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
287 { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
288 { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
291 { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
292 { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
293 { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
294 { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
295 { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
296 { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
297 { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
298 { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
299 { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
300 { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
306 { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
307 { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
308 { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
309 { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
310 { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
311 { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
312 { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" },
317 { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
318 { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
324 NULL,
329 NULL,
334 NULL,
338 { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
339 { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
340 { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
341 { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
353 NULL,
359 NULL,
364 NULL,
372 { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
373 { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
386 NULL,
391 NULL,
399 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
400 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
407 NULL,
415 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
422 NULL,
427 NULL,
432 NULL,
437 NULL,
443 NULL,
449 NULL,
453 { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
454 { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
455 { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
456 { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
457 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
458 { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
459 { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
460 { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
461 { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
462 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
463 { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
468 { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
469 { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
470 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
476 NULL,
480 { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
486 NULL,
490 { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
500 { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
501 { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
507 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
512 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
517 { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
518 { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
521 { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
522 { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
548 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
549 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
550 DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
551 DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
552 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
553 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
554 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
555 DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
556 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
557 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
558 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
559 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
560 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
561 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
562 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
563 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
564 DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
565 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
566 DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
567 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
568 DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
569 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
570 DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
571 DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
572 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
573 DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
574 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
575 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
576 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
577 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
578 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
579 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
580 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
581 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
582 DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
583 DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
584 DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
585 DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
586 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
587 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
588 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
589 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
590 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
591 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
592 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
593 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
594 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
595 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
596 DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
597 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
598 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
599 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
600 DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
601 DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
602 { .node_name = NULL },
616 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
617 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
619 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
625 abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
631 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
636 usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");