Lines Matching defs:clock
191 "clock-output-names",
206 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
214 d->clocks[index].clk = clock;
221 dev_warn(d->dev, "clock %s con_id lookup may fail\n",
224 cl = clkdev_create(clock, con_id, NULL);
229 dev_warn(d->dev, "no con_id for clock %s\n", name);
235 d->outputs.clks[output_index] = clock;
251 struct clk *clock;
258 clock = clk_register_divider(d->dev, child_name, parent_name, 0,
261 if (IS_ERR(clock)) {
263 name, PTR_ERR(clock));
264 return PTR_ERR(clock);
267 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
280 struct clk *clock;
287 clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
289 if (IS_ERR(clock)) {
291 name, PTR_ERR(clock));
292 return PTR_ERR(clock);
295 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
309 struct clk *clock;
316 clock = clk_register_gate(d->dev, child_name, parent_name, 0,
319 if (IS_ERR(clock)) {
321 name, PTR_ERR(clock));
322 return PTR_ERR(clock);
325 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
338 struct clk *clock;
345 clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
347 if (IS_ERR(clock))
348 return PTR_ERR(clock);
350 return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
389 * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
441 * Note that the DCO clock is never subject to bypass: if the PLL is off,
494 struct clk *clock;
525 /* Internal input clock divider N2 */
533 clock = devm_clk_register(d->dev, &d->dco.hw);
534 if (IS_ERR(clock))
535 return PTR_ERR(clock);
537 return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
590 struct clk *clock;
599 "clock-output-names",
629 clock = devm_clk_register(d->dev, &co->hw);
630 if (IS_ERR(clock)) {
632 name, PTR_ERR(clock));
633 return PTR_ERR(clock);
636 return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
709 /* Output clock dcoclkldo is the DCO */
811 struct clk *clock;
821 clock = devm_clk_get(d->dev, d->parent_names[0]);
822 if (IS_ERR(clock)) {
824 return PTR_ERR(clock);
826 d->parent_clocks[TI_ADPLL_CLKINP] = clock;
828 clock = devm_clk_get(d->dev, d->parent_names[1]);
829 if (IS_ERR(clock)) {
830 dev_err(d->dev, "could not get clkinpulow clock\n");
831 return PTR_ERR(clock);
833 d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
836 clock = devm_clk_get(d->dev, d->parent_names[2]);
837 if (IS_ERR(clock)) {
838 dev_err(d->dev, "could not get clkinphif clock\n");
839 return PTR_ERR(clock);
841 d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
862 { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
863 { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
977 MODULE_ALIAS("platform:dm814-adpll-clock");