Lines Matching defs:clk_base
372 * @clk_base: address of CAR controller
379 void __iomem *clk_base;
405 void __iomem *clk_base, void __iomem *pmc,
410 void __iomem *clk_base, void __iomem *pmc,
415 void __iomem *clk_base, void __iomem *pmc,
421 void __iomem *clk_base, void __iomem *pmc,
427 void __iomem *clk_base, void __iomem *pmc,
433 void __iomem *clk_base, void __iomem *pmc,
439 const char *parent_name, void __iomem *clk_base,
446 void __iomem *clk_base, unsigned long flags,
452 void __iomem *clk_base, unsigned long flags,
457 const char *parent_name, void __iomem *clk_base,
463 const char *parent_name, void __iomem *clk_base,
469 void __iomem *clk_base, unsigned long flags,
474 void __iomem *clk_base, void __iomem *pmc,
480 void __iomem *clk_base, unsigned long flags,
486 void __iomem *clk_base, unsigned long flags,
492 void __iomem *clk_base, unsigned long flags,
547 * @clk_base: address of CAR controller
567 void __iomem *clk_base;
588 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
639 struct tegra_clk_periph *periph, void __iomem *clk_base,
643 struct tegra_clk_periph *periph, void __iomem *clk_base,
720 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
799 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
856 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
863 void tegra_audio_clk_init(void __iomem *clk_base,
868 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
873 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
877 void tegra_super_clk_gen4_init(void __iomem *clk_base,
880 void tegra_super_clk_gen5_init(void __iomem *clk_base,
909 void tegra_clk_osc_resume(void __iomem *clk_base);