Lines Matching defs:clk_base
148 static void __iomem *clk_base;
816 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
822 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
825 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
830 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
836 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
839 clk_base + PLLM_OUT, 1, 0,
844 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
854 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
859 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
869 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
882 clk_base + PLLE_AUX, 2, 1, 0, NULL);
883 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
908 clk_base + SUPER_CCLKG_DIVIDER, 0,
917 clk_base + SUPER_CCLKG_DIVIDER, 0,
926 clk_base + SUPER_CCLKG_DIVIDER, 0,
934 clk_base + CCLKG_BURST_POLICY,
943 clk_base + SUPER_CCLKLP_DIVIDER, 0,
952 clk_base + SUPER_CCLKLP_DIVIDER, 0,
961 clk_base + SUPER_CCLKLP_DIVIDER, 0,
969 clk_base + CCLKLP_BURST_POLICY,
978 clk_base + SCLK_BURST_POLICY,
987 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1026 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1031 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1036 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1041 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);
1045 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1050 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1055 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1061 clk = tegra_clk_register_periph_data(clk_base, data);
1070 clk_base, data->offset);
1074 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1083 reg = readl(clk_base +
1094 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1101 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1110 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1111 reg = readl(clk_base +
1119 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1121 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1130 cpu_rst_status = readl(clk_base +
1146 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1147 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
1150 readl(clk_base + CLK_RESET_CCLK_BURST);
1152 readl(clk_base + CLK_RESET_PLLX_BASE);
1154 readl(clk_base + CLK_RESET_PLLX_MISC);
1156 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1165 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1176 misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);
1177 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);
1183 clk_base + CLK_RESET_PLLX_MISC);
1185 clk_base + CLK_RESET_PLLX_BASE);
1198 clk_base + CLK_RESET_CCLK_DIVIDER);
1200 clk_base + CLK_RESET_CCLK_BURST);
1203 clk_base + CLK_RESET_SOURCE_CSITE);
1324 clk_base = of_iomap(np, 0);
1325 if (!clk_base) {
1342 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1347 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1356 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,