Lines Matching refs:params
688 struct tegra_clk_pll_params *params,
691 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
699 params->defaults_set = false;
708 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
713 _pll_misc_chk_default(clk_base, params, 0, default_val,
717 _pll_misc_chk_default(clk_base, params, 1, default_val,
721 _pll_misc_chk_default(clk_base, params, 2, default_val,
725 _pll_misc_chk_default(clk_base, params, 3, default_val,
732 pllcx->params->defaults_set = true;
734 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
736 pllcx_check_defaults(pllcx->params);
737 if (!pllcx->params->defaults_set)
745 clk_base + pllcx->params->ext_misc_reg[0]);
747 clk_base + pllcx->params->ext_misc_reg[1]);
749 clk_base + pllcx->params->ext_misc_reg[2]);
751 clk_base + pllcx->params->ext_misc_reg[3]);
783 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
785 plla->params->defaults_set = true;
794 plla->params->defaults_set = false;
801 _pll_misc_chk_default(clk_base, plla->params, 0, val,
805 _pll_misc_chk_default(clk_base, plla->params, 2, val,
809 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
812 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
820 writel_relaxed(val, clk_base + plla->params->base_reg);
822 clk_base + plla->params->ext_misc_reg[0]);
824 clk_base + plla->params->ext_misc_reg[2]);
837 plld->params->defaults_set = true;
839 if (readl_relaxed(clk_base + plld->params->base_reg) &
847 _pll_misc_chk_default(clk_base, plld->params, 1,
854 _pll_misc_chk_default(clk_base, plld->params, 0, val,
857 if (!plld->params->defaults_set)
862 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
865 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
871 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
875 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
877 plld->params->ext_misc_reg[1]);
889 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
891 plldss->params->defaults_set = true;
901 plldss->params->defaults_set = false;
906 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
915 if (plldss->params->ssc_ctrl_en_mask) {
917 _pll_misc_chk_default(clk_base, plldss->params, 1,
920 _pll_misc_chk_default(clk_base, plldss->params, 2,
923 _pll_misc_chk_default(clk_base, plldss->params, 3,
925 } else if (plldss->params->ext_misc_reg[1]) {
927 _pll_misc_chk_default(clk_base, plldss->params, 1,
932 if (!plldss->params->defaults_set)
940 plldss->params->base_reg);
943 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
946 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
955 writel_relaxed(val, clk_base + plldss->params->base_reg);
958 if (!plldss->params->ext_misc_reg[1]) {
960 plldss->params->ext_misc_reg[0]);
966 plldss->params->ext_misc_reg[0]);
969 clk_base + plldss->params->ext_misc_reg[1]);
970 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
971 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
1008 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
1010 pllre->params->defaults_set = true;
1023 pllre->params->defaults_set = false;
1029 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1033 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1040 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1043 if (!pllre->params->defaults_set)
1052 writel_relaxed(val, clk_base + pllre->params->base_reg);
1054 clk_base + pllre->params->ext_misc_reg[0]);
1098 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1102 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1107 _pll_misc_chk_default(clk_base, pll->params, 2,
1111 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1115 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1119 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1128 pllx->params->defaults_set = true;
1137 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1145 if (!pllx->params->defaults_set)
1148 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1151 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1154 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1162 pllx->params->ext_misc_reg[0]);
1166 pllx->params->ext_misc_reg[1]);
1169 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1173 pllx->params->ext_misc_reg[3]);
1177 pllx->params->ext_misc_reg[4]);
1179 pllx->params->ext_misc_reg[5]);
1186 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1188 pllmb->params->defaults_set = true;
1198 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1201 if (!pllmb->params->defaults_set)
1204 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1207 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1215 clk_base + pllmb->params->ext_misc_reg[0]);
1234 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1240 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1247 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1249 pllp->params->defaults_set = true;
1258 if (!pllp->params->defaults_set)
1262 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1266 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1274 clk_base + pllp->params->ext_misc_reg[0]);
1277 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1281 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1291 static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1299 _pll_misc_chk_default(clk_base, params, 0, val,
1304 _pll_misc_chk_default(clk_base, params, 1, val,
1348 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1349 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1350 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1351 mask(p->params->div_nmp->divp_width))
1353 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1354 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1355 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1368 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1384 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1387 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1390 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1393 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1395 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1398 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1401 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1403 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1404 writel_relaxed(base, clk_base + pllx->params->base_reg);
1408 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1414 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1432 struct tegra_clk_pll_params *params = pll->params;
1440 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1441 p = DIV_ROUND_UP(params->vco_min, rate);
1442 p = params->round_p_to_pdiv(p, &pdiv);
1444 p = rate >= params->vco_min ? 1 : -EINVAL;
1457 if (p_rate > params->vco_max)
1458 p_rate = params->vco_max;
1464 if (params->sdm_ctrl_reg) {
1467 if (rem || params->ssc_ctrl_reg) {
1504 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1507 unsigned long vco_min = params->vco_min;
1509 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1510 vco_min = min(vco_min, params->vco_min);
2859 pllu.params = &pll_u_vco_params;
2860 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2861 reg &= ~BIT(pllu.params->iddq_bit_idx);
2862 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);