Lines Matching defs:enabled
269 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
738 pr_warn("%s already enabled. Postponing set full defaults\n",
793 pr_warn("PLL_A boot enabled with IDDQ set\n");
797 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
858 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
900 pr_warn("plldss boot enabled with IDDQ set\n");
933 pr_warn("%s already enabled. Postponing set full defaults\n",
1035 pr_warn("unexpected IDDQ bit set for enabled clock\n");
1044 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
1146 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
1202 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
1225 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
1229 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
1232 if (!enabled)
1259 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1322 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1466 /* If ssc is enabled SDM enabled as well, even for integer n */
3436 * be enabled prior to changing its clock source and divider to
3449 /* wait for all writes to happen to have all the clocks enabled */