Lines Matching defs:clk_base
298 static void __iomem *clk_base;
496 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
501 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
509 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
511 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
519 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
523 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
531 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
533 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
541 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
553 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
562 writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset);
568 writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL);
574 writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC);
582 val = readl_relaxed(clk_base + mbist->lvl2_offset);
583 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
584 fence_udelay(1, clk_base);
585 writel_relaxed(val, clk_base + mbist->lvl2_offset);
586 fence_udelay(1, clk_base);
596 csi_src = readl_relaxed(clk_base + PLLD_BASE);
597 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
598 fence_udelay(1, clk_base);
600 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
601 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
602 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
603 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
604 fence_udelay(1, clk_base);
606 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
607 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
608 writel_relaxed(csi_src, clk_base + PLLD_BASE);
609 fence_udelay(1, clk_base);
618 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
619 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
620 fence_udelay(1, clk_base);
628 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
629 fence_udelay(1, clk_base);
636 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
637 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
638 fence_udelay(1, clk_base);
648 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
649 fence_udelay(1, clk_base);
658 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
659 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
660 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
662 clk_base + LVL2_CLK_GATE_OVRE);
663 fence_udelay(1, clk_base);
682 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
683 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
684 fence_udelay(1, clk_base);
713 _pll_misc_chk_default(clk_base, params, 0, default_val,
717 _pll_misc_chk_default(clk_base, params, 1, default_val,
721 _pll_misc_chk_default(clk_base, params, 2, default_val,
725 _pll_misc_chk_default(clk_base, params, 3, default_val,
734 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
745 clk_base + pllcx->params->ext_misc_reg[0]);
747 clk_base + pllcx->params->ext_misc_reg[1]);
749 clk_base + pllcx->params->ext_misc_reg[2]);
751 clk_base + pllcx->params->ext_misc_reg[3]);
783 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
801 _pll_misc_chk_default(clk_base, plla->params, 0, val,
805 _pll_misc_chk_default(clk_base, plla->params, 2, val,
809 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
812 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
820 writel_relaxed(val, clk_base + plla->params->base_reg);
822 clk_base + plla->params->ext_misc_reg[0]);
824 clk_base + plla->params->ext_misc_reg[2]);
839 if (readl_relaxed(clk_base + plld->params->base_reg) &
847 _pll_misc_chk_default(clk_base, plld->params, 1,
854 _pll_misc_chk_default(clk_base, plld->params, 0, val,
862 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
865 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
871 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
875 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
876 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
889 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
906 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
917 _pll_misc_chk_default(clk_base, plldss->params, 1,
920 _pll_misc_chk_default(clk_base, plldss->params, 2,
923 _pll_misc_chk_default(clk_base, plldss->params, 3,
927 _pll_misc_chk_default(clk_base, plldss->params, 1,
939 writel_relaxed(val, clk_base +
943 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
946 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
955 writel_relaxed(val, clk_base + plldss->params->base_reg);
959 writel_relaxed(misc0_val, clk_base +
965 writel_relaxed(misc0_val, clk_base +
969 clk_base + plldss->params->ext_misc_reg[1]);
970 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
971 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
1008 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
1029 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1033 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1040 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1052 writel_relaxed(val, clk_base + pllre->params->base_reg);
1054 clk_base + pllre->params->ext_misc_reg[0]);
1098 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1102 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1107 _pll_misc_chk_default(clk_base, pll->params, 2,
1111 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1115 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1119 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1137 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1148 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1151 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1154 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1161 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
1165 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
1169 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1172 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
1176 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
1178 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
1186 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1198 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1204 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1207 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1215 clk_base + pllmb->params->ext_misc_reg[0]);
1234 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1240 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1247 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1262 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1266 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1274 clk_base + pllp->params->ext_misc_reg[0]);
1277 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1281 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1299 _pll_misc_chk_default(clk_base, params, 0, val,
1304 _pll_misc_chk_default(clk_base, params, 1, val,
1310 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1325 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1328 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1330 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1333 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1341 clk_base + pllu->ext_misc_reg[0]);
1343 clk_base + pllu->ext_misc_reg[1]);
1370 val = readl_relaxed(clk_base + reg);
1387 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1390 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1393 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1395 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1401 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1404 writel_relaxed(base, clk_base + pllx->params->base_reg);
1408 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
2728 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2736 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2744 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2746 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2766 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2768 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2772 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2782 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2785 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2796 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2799 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2802 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2807 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2814 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2817 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2820 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2822 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2825 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2829 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2831 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2836 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2838 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2860 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2862 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2863 fence_udelay(5, clk_base);
2865 reg = readl_relaxed(clk_base + PLLU_BASE);
2870 writel(reg, clk_base + PLLU_BASE);
2871 fence_udelay(1, clk_base);
2873 writel(reg, clk_base + PLLU_BASE);
2897 reg = readl_relaxed(clk_base + PLLU_BASE);
2907 reg = readl_relaxed(clk_base + PLLU_BASE);
2909 writel(reg, clk_base + PLLU_BASE);
2911 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2917 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2919 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2921 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2922 fence_udelay(1, clk_base);
2924 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2926 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2927 fence_udelay(1, clk_base);
2929 reg = readl_relaxed(clk_base + PLLU_BASE);
2931 writel_relaxed(reg, clk_base + PLLU_BASE);
2935 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2990 clk_base + CLK_SOURCE_EMC,
3039 void __iomem *clk_base,
3050 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
3054 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
3058 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
3064 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
3069 clk_base, 0, 48,
3075 clk_base, 0, 82,
3081 CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,
3088 ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
3093 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3099 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3105 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
3109 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3114 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3129 clk = tegra_clk_register_periph_data(clk_base, init);
3133 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
3136 clk = tegra210_clk_register_emc(np, clk_base);
3143 static void __init tegra210_pll_init(void __iomem *clk_base,
3149 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3157 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3160 clk_base + PLLC_OUT, 1, 0,
3172 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3178 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3184 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3190 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3222 clk_base + PLLU_BASE, 16, 4, 0,
3229 clk_base + PLLU_OUTA, 0,
3233 clk_base + PLLU_OUTA, 1, 0,
3240 clk_base + PLLU_OUTA, 0,
3244 clk_base + PLLU_OUTA, 17, 16,
3251 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3258 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3265 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3271 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3284 clk_base, pmc, 0,
3291 clk_base + PLLRE_BASE, 16, 5, 0,
3297 clk_base + PLLRE_OUT1, 0,
3301 clk_base + PLLRE_OUT1, 1, 0,
3307 clk_base, 0, &pll_e_params, NULL);
3312 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3319 clk_base + PLLC4_BASE, 19, 4, 0,
3338 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3341 clk_base + PLLC4_OUT, 1, 0,
3347 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3353 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3378 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
3389 #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
3391 writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
3406 spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
3407 misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
3408 clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
3421 tegra_clk_osc_resume(clk_base);
3427 writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
3428 writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
3429 writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
3441 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L);
3442 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H);
3443 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U);
3444 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V);
3445 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W);
3446 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X);
3447 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y);
3450 fence_udelay(2, clk_base);
3464 readl(clk_base + CLK_SOURCE_CSITE);
3465 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
3471 clk_base + CLK_SOURCE_CSITE);
3574 readl_relaxed(clk_base + RST_DFLL_DVCO);
3586 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3588 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3602 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3604 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3614 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3626 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3634 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3686 clk_base = of_iomap(np, 0);
3687 if (!clk_base) {
3725 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
3730 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3733 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
3739 tegra210_pll_init(clk_base, pmc_base);
3740 tegra210_periph_clk_init(np, clk_base, pmc_base);
3741 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3746 value = readl(clk_base + PLLD_BASE);
3748 writel(value, clk_base + PLLD_BASE);
3752 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,