Lines Matching defs:clk
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
16 #include <linux/clk/tegra.h>
22 #include "clk.h"
23 #include "clk-id.h"
29 * periph_regs[] in drivers/clk/tegra/clk.c
296 static struct clk **clks;
1063 if (!IS_ERR_OR_NULL(hw->clk))
1412 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
2986 struct clk *clk;
2988 clk = clk_register_divider_table(NULL, name, parent_name,
2993 clks[TEGRA210_CLK_MC] = clk;
3042 struct clk *clk;
3046 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
3048 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
3050 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
3052 clks[TEGRA210_CLK_SOR_SAFE] = clk;
3054 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
3056 clks[TEGRA210_CLK_DPAUX] = clk;
3058 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
3060 clks[TEGRA210_CLK_DPAUX1] = clk;
3063 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
3065 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
3068 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
3071 clks[TEGRA210_CLK_DSIA] = clk;
3074 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
3077 clks[TEGRA210_CLK_DSIB] = clk;
3080 clk = clk_register_gate(NULL, "csi_tpg", "pll_d",
3083 clk_register_clkdev(clk, "csi_tpg", NULL);
3084 clks[TEGRA210_CLK_CSI_TPG] = clk;
3087 clk = tegra_clk_register_periph("la", la_parents,
3090 clks[TEGRA210_CLK_LA] = clk;
3093 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3095 clk_register_clkdev(clk, "cml0", NULL);
3096 clks[TEGRA210_CLK_CML0] = clk;
3099 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3101 clk_register_clkdev(clk, "cml1", NULL);
3102 clks[TEGRA210_CLK_CML1] = clk;
3104 clk = tegra_clk_register_super_clk("aclk", aclk_parents,
3107 clks[TEGRA210_CLK_ACLK] = clk;
3109 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3112 clks[TEGRA210_CLK_SDMMC2] = clk;
3114 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3117 clks[TEGRA210_CLK_SDMMC4] = clk;
3121 struct clk **clkp;
3129 clk = tegra_clk_register_periph_data(clk_base, init);
3130 *clkp = clk;
3136 clk = tegra210_clk_register_emc(np, clk_base);
3137 clks[TEGRA210_CLK_EMC] = clk;
3146 struct clk *clk;
3149 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3151 if (!WARN_ON(IS_ERR(clk)))
3152 clk_register_clkdev(clk, "pll_c", NULL);
3153 clks[TEGRA210_CLK_PLL_C] = clk;
3156 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
3159 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
3162 clk_register_clkdev(clk, "pll_c_out1", NULL);
3163 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
3166 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
3168 clk_register_clkdev(clk, "pll_c_ud", NULL);
3169 clks[TEGRA210_CLK_PLL_C_UD] = clk;
3172 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3174 clk_register_clkdev(clk, "pll_c2", NULL);
3175 clks[TEGRA210_CLK_PLL_C2] = clk;
3178 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3180 clk_register_clkdev(clk, "pll_c3", NULL);
3181 clks[TEGRA210_CLK_PLL_C3] = clk;
3184 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3186 clk_register_clkdev(clk, "pll_m", NULL);
3187 clks[TEGRA210_CLK_PLL_M] = clk;
3190 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3192 clk_register_clkdev(clk, "pll_mb", NULL);
3193 clks[TEGRA210_CLK_PLL_MB] = clk;
3196 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
3198 clk_register_clkdev(clk, "pll_m_ud", NULL);
3199 clks[TEGRA210_CLK_PLL_M_UD] = clk;
3202 clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb",
3204 clk_register_clkdev(clk, "pll_mb_ud", NULL);
3205 clks[TEGRA210_CLK_PLL_MB_UD] = clk;
3208 clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p",
3210 clks[TEGRA210_CLK_PLL_P_UD] = clk;
3214 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
3216 clk_register_clkdev(clk, "pll_u_vco", NULL);
3217 clks[TEGRA210_CLK_PLL_U] = clk;
3221 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
3224 clk_register_clkdev(clk, "pll_u_out", NULL);
3225 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
3228 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
3232 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
3235 clk_register_clkdev(clk, "pll_u_out1", NULL);
3236 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
3239 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
3243 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
3246 clk_register_clkdev(clk, "pll_u_out2", NULL);
3247 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
3250 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
3253 clk_register_clkdev(clk, "pll_u_480M", NULL);
3254 clks[TEGRA210_CLK_PLL_U_480M] = clk;
3257 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
3260 clk_register_clkdev(clk, "pll_u_60M", NULL);
3261 clks[TEGRA210_CLK_PLL_U_60M] = clk;
3264 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
3267 clk_register_clkdev(clk, "pll_u_48M", NULL);
3268 clks[TEGRA210_CLK_PLL_U_48M] = clk;
3271 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3273 clk_register_clkdev(clk, "pll_d", NULL);
3274 clks[TEGRA210_CLK_PLL_D] = clk;
3277 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
3279 clk_register_clkdev(clk, "pll_d_out0", NULL);
3280 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
3283 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",
3287 clk_register_clkdev(clk, "pll_re_vco", NULL);
3288 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
3290 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
3293 clk_register_clkdev(clk, "pll_re_out", NULL);
3294 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
3296 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",
3300 clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",
3303 clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;
3306 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
3308 clk_register_clkdev(clk, "pll_e", NULL);
3309 clks[TEGRA210_CLK_PLL_E] = clk;
3312 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3314 clk_register_clkdev(clk, "pll_c4_vco", NULL);
3315 clks[TEGRA210_CLK_PLL_C4] = clk;
3318 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
3321 clk_register_clkdev(clk, "pll_c4_out0", NULL);
3322 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
3325 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
3327 clk_register_clkdev(clk, "pll_c4_out1", NULL);
3328 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
3331 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
3333 clk_register_clkdev(clk, "pll_c4_out2", NULL);
3334 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
3337 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
3340 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
3343 clk_register_clkdev(clk, "pll_c4_out3", NULL);
3344 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
3347 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3349 clk_register_clkdev(clk, "pll_dp", NULL);
3350 clks[TEGRA210_CLK_PLL_DP] = clk;
3353 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3355 clk_register_clkdev(clk, "pll_d2", NULL);
3356 clks[TEGRA210_CLK_PLL_D2] = clk;
3359 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
3361 clk_register_clkdev(clk, "pll_d2_out0", NULL);
3362 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
3365 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
3367 clk_register_clkdev(clk, "pll_p_out2", NULL);
3368 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
3660 struct clk *clk = clks[clk_id];
3662 if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {
3667 clk_data[j].clk = clk;