Lines Matching defs:pll_ref_div
574 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
579 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
583 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
587 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
591 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
606 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
609 switch (pll_ref_div) {
617 pr_err("Invalid pll ref divider %d\n", pll_ref_div);
864 unsigned int pll_ref_div;
874 pll_ref_div = tegra20_get_pll_ref_div();
876 CLK_SET_RATE_PARENT, 1, pll_ref_div);