Lines Matching defs:clk_base
130 static void __iomem *clk_base;
572 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
606 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
628 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
634 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
637 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
642 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
648 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
651 clk_base + PLLM_OUT, 1, 0,
656 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
661 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
666 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
676 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
682 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
685 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
690 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
709 clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK,
717 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
737 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
739 clk_base + AUDIO_SYNC_CLK, 4,
747 TEGRA_PERIPH_NO_RESET, clk_base,
797 clk_base, 0, 3, periph_clk_enb_refcnt);
801 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);
805 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
810 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
816 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
822 0, clk_base + MISC_CLK_ENB, 22, 2,
828 0, clk_base + MISC_CLK_ENB, 20, 2,
834 clk_base, 0, 94, periph_clk_enb_refcnt);
839 clk_base, 0, 93, periph_clk_enb_refcnt);
844 clk = tegra_clk_register_periph_data(clk_base, data);
853 clk_base, data->offset);
857 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
886 reg = readl(clk_base +
897 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
904 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
912 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
914 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
916 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
923 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
925 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
933 cpu_rst_status = readl(clk_base +
943 readl(clk_base + CLK_SOURCE_CSITE);
944 writel(3<<30, clk_base + CLK_SOURCE_CSITE);
947 readl(clk_base + CCLK_BURST_POLICY);
949 readl(clk_base + PLLX_BASE);
951 readl(clk_base + PLLX_MISC);
953 readl(clk_base + SUPER_CCLK_DIVIDER);
962 reg = readl(clk_base + CCLK_BURST_POLICY);
973 misc = readl_relaxed(clk_base + PLLX_MISC);
974 base = readl_relaxed(clk_base + PLLX_BASE);
980 clk_base + PLLX_MISC);
982 clk_base + PLLX_BASE);
995 clk_base + SUPER_CCLK_DIVIDER);
997 clk_base + CCLK_BURST_POLICY);
1000 clk_base + CLK_SOURCE_CSITE);
1118 clk_base = of_iomap(np, 0);
1119 if (!clk_base) {
1137 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
1146 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);