Lines Matching refs:val
57 u32 val, div;
59 val = readl_relaxed(emc->reg);
60 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
75 u32 val, div;
77 val = readl_relaxed(emc->reg);
78 val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
79 val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
81 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
84 val |= USE_PLLM_UD;
86 val &= ~USE_PLLM_UD;
89 val |= MC_EMC_SAME_FREQ;
91 val &= ~MC_EMC_SAME_FREQ;
93 writel_relaxed(val, emc->reg);
105 u32 val, div;
109 val = readl_relaxed(emc->reg);
110 val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
111 val |= div;
113 index = val >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
116 val |= USE_PLLM_UD;
118 val &= ~USE_PLLM_UD;
121 val |= MC_EMC_SAME_FREQ;
123 val &= ~MC_EMC_SAME_FREQ;
125 writel_relaxed(val, emc->reg);
138 u32 val, div;
142 val = readl_relaxed(emc->reg);
144 val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
145 val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
147 val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
148 val |= div;
151 val |= USE_PLLM_UD;
153 val &= ~USE_PLLM_UD;
156 val |= MC_EMC_SAME_FREQ;
158 val &= ~MC_EMC_SAME_FREQ;
160 writel_relaxed(val, emc->reg);