Lines Matching defs:clk_base
119 static void __iomem *clk_base;
1024 static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1035 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
1040 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1044 clk_base, 0, 48,
1049 clk_base, 0, 82,
1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1079 clk = tegra_clk_register_periph_data(clk_base, init);
1083 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1086 static void __init tegra124_pll_init(void __iomem *clk_base,
1092 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1099 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1102 clk_base + PLLC_OUT, 1, 0,
1114 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1120 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1126 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1133 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1136 clk_base + PLLM_OUT, 1, 0,
1148 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
1155 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1179 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1191 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1197 clk_base + PLLRE_BASE, 16, 4, 0,
1204 clk_base, 0, &pll_e_params, NULL);
1209 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1215 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1221 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1240 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1255 readl(clk_base + CLK_SOURCE_CSITE);
1256 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1259 readl(clk_base + CCLKG_BURST_POLICY);
1261 readl(clk_base + CCLKG_BURST_POLICY + 4);
1267 clk_base + CLK_SOURCE_CSITE);
1270 clk_base + CCLKG_BURST_POLICY);
1272 clk_base + CCLKG_BURST_POLICY + 4);
1379 readl_relaxed(clk_base + RST_DFLL_DVCO);
1391 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1393 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1407 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1409 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1460 clk_base = of_iomap(np, 0);
1461 if (!clk_base) {
1480 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1485 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1491 tegra124_pll_init(clk_base, pmc_base);
1492 tegra124_periph_clk_init(clk_base, pmc_base);
1493 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
1498 plld_base = readl(clk_base + PLLD_BASE);
1500 writel(plld_base, clk_base + PLLD_BASE);
1510 * tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
1515 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1521 clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np,