Lines Matching refs:timing
47 * When we change the timing to a timing with a parent that has the same
49 * timing that has a different clock source.
116 struct emc_timing *timing = NULL;
132 timing = tegra->timings + i;
134 if (timing->rate < req->rate && i != t - 1)
137 if (timing->rate > req->max_rate) {
143 if (timing->rate < req->min_rate)
146 req->rate = timing->rate;
150 if (timing) {
151 req->rate = timing->rate;
203 struct emc_timing *timing)
214 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
215 timing->parent_rate, __clk_get_name(timing->parent));
217 if (emc_get_parent(&tegra->hw) == timing->parent_index &&
218 clk_get_rate(timing->parent) != timing->parent_rate) {
220 __clk_get_name(timing->parent),
221 clk_get_rate(timing->parent),
222 timing->parent_rate);
228 err = clk_set_rate(timing->parent, timing->parent_rate);
231 __clk_get_name(timing->parent), timing->parent_rate,
237 err = clk_prepare_enable(timing->parent);
243 div = timing->parent_rate / (timing->rate / 2) - 2;
245 err = tegra_emc_prepare_timing_change(emc, timing->rate);
254 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
263 tegra_emc_complete_timing_change(emc, timing->rate);
265 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
268 tegra->prev_parent = timing->parent;
275 * Get backup timing to use as an intermediate step when a change between
277 * find a timing with a higher clock rate to avoid a rate below any set rate
285 struct emc_timing *timing;
288 timing = tegra->timings + i;
289 if (timing->ram_code != ram_code)
292 if (emc_parent_clk_sources[timing->parent_index] !=
295 return timing;
299 timing = tegra->timings + i;
300 if (timing->ram_code != ram_code)
303 if (emc_parent_clk_sources[timing->parent_index] !=
306 return timing;
316 struct emc_timing *timing = NULL;
336 timing = tegra->timings + i;
341 if (!timing) {
347 emc_parent_clk_sources[timing->parent_index] &&
348 clk_get_rate(timing->parent) != timing->parent_rate) {
358 pr_err("cannot find backup timing\n");
367 pr_err("cannot set backup timing: %d\n", err);
372 return emc_set_timing(tegra, timing);
378 struct emc_timing *timing,
386 pr_err("timing %pOF: failed to read rate\n", node);
390 timing->rate = tmp;
394 pr_err("timing %pOF: failed to read parent rate\n", node);
398 timing->parent_rate = tmp;
400 timing->parent = of_clk_get_by_name(node, "emc-parent");
401 if (IS_ERR(timing->parent)) {
402 pr_err("timing %pOF: failed to get parent clock\n", node);
403 return PTR_ERR(timing->parent);
406 timing->parent_index = 0xff;
408 __clk_get_name(timing->parent));
410 pr_err("timing %pOF: %s is not a valid parent\n",
411 node, __clk_get_name(timing->parent));
412 clk_put(timing->parent);
416 timing->parent_index = i;
453 struct emc_timing *timing = timings_ptr + (i++);
455 err = load_one_timing_from_dt(tegra, timing, child);
462 timing->ram_code = ram_code;