Lines Matching refs:tegra
3 * drivers/clk/tegra/clk-emc.c
23 #include <soc/tegra/fuse.h>
24 #include <soc/tegra/emc.h>
90 struct tegra_clk_emc *tegra;
93 tegra = container_of(hw, struct tegra_clk_emc, hw);
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
114 struct tegra_clk_emc *tegra;
119 tegra = container_of(hw, struct tegra_clk_emc, hw);
121 for (k = 0; k < tegra->num_timings; k++) {
122 if (tegra->timings[k].ram_code == ram_code)
126 for (t = k; t < tegra->num_timings; t++) {
127 if (tegra->timings[t].ram_code != ram_code)
132 timing = tegra->timings + i;
139 req->rate = tegra->timings[i - 1].rate;
161 struct tegra_clk_emc *tegra;
164 tegra = container_of(hw, struct tegra_clk_emc, hw);
166 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
172 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
176 if (tegra->emc)
177 return tegra->emc;
179 if (!tegra->emc_node)
182 pdev = of_find_device_by_node(tegra->emc_node);
189 of_node_put(tegra->emc_node);
190 tegra->emc_node = NULL;
192 tegra->emc = platform_get_drvdata(pdev);
193 if (!tegra->emc) {
199 return tegra->emc;
202 static int emc_set_timing(struct tegra_clk_emc *tegra,
209 struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
217 if (emc_get_parent(&tegra->hw) == timing->parent_index &&
226 tegra->changing_timing = true;
249 spin_lock_irqsave(tegra->lock, flags);
251 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
259 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
261 spin_unlock_irqrestore(tegra->lock, flags);
265 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
266 clk_disable_unprepare(tegra->prev_parent);
268 tegra->prev_parent = timing->parent;
269 tegra->changing_timing = false;
280 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
287 for (i = timing_index+1; i < tegra->num_timings; i++) {
288 timing = tegra->timings + i;
294 tegra->timings[timing_index].parent_index])
299 timing = tegra->timings + i;
305 tegra->timings[timing_index].parent_index])
315 struct tegra_clk_emc *tegra;
320 tegra = container_of(hw, struct tegra_clk_emc, hw);
330 if (tegra->changing_timing)
333 for (i = 0; i < tegra->num_timings; i++) {
334 if (tegra->timings[i].rate == rate &&
335 tegra->timings[i].ram_code == ram_code) {
336 timing = tegra->timings + i;
356 backup_timing = get_backup_timing(tegra, i);
365 err = emc_set_timing(tegra, backup_timing);
372 return emc_set_timing(tegra, timing);
377 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
433 static int load_timings_from_dt(struct tegra_clk_emc *tegra,
443 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);
445 tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
446 if (!tegra->timings)
449 timings_ptr = tegra->timings + tegra->num_timings;
450 tegra->num_timings += child_count;
455 err = load_one_timing_from_dt(tegra, timing, child);
458 kfree(tegra->timings);
481 struct tegra_clk_emc *tegra;
488 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
489 if (!tegra)
492 tegra->clk_regs = base;
493 tegra->lock = lock;
495 tegra->num_timings = 0;
507 err = load_timings_from_dt(tegra, node, node_ram_code);
510 kfree(tegra);
515 if (tegra->num_timings == 0)
518 tegra->emc_node = of_parse_phandle(np,
520 if (!tegra->emc_node)
529 tegra->hw.init = &init;
531 clk = clk_register(NULL, &tegra->hw);
535 tegra->prev_parent = clk_hw_get_parent_by_index(
536 &tegra->hw, emc_get_parent(&tegra->hw))->clk;
537 tegra->changing_timing = false;
540 clk_register_clkdev(clk, "emc", "tegra-clk-debug");