Lines Matching refs:val
37 u32 val, state;
40 val = readl_relaxed(mux->reg);
42 state = val & SUPER_STATE_MASK;
50 source = (val >> shift) & super_state_to_src_mask(mux);
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&
66 u32 val, state;
74 val = readl_relaxed(mux->reg);
75 state = val & SUPER_STATE_MASK;
96 val ^= SUPER_LP_DIV2_BYPASS;
97 writel_relaxed(val, mux->reg);
109 val &= ~((super_state_to_src_mask(mux)) << shift);
110 val |= (index & (super_state_to_src_mask(mux))) << shift;
112 writel_relaxed(val, mux->reg);