Lines Matching defs:super
83 * For LP mode super-clock switch between PLLX direct
147 struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
148 struct clk_hw *div_hw = &super->frac_div.hw;
152 return super->div_ops->round_rate(div_hw, rate, parent_rate);
158 struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
159 struct clk_hw *div_hw = &super->frac_div.hw;
163 return super->div_ops->recalc_rate(div_hw, parent_rate);
169 struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
170 struct clk_hw *div_hw = &super->frac_div.hw;
174 return super->div_ops->set_rate(div_hw, rate, parent_rate);
179 struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
180 struct clk_hw *div_hw = &super->frac_div.hw;
187 super->div_ops->restore_context(div_hw);
205 struct tegra_clk_super_mux *super;
209 super = kzalloc(sizeof(*super), GFP_KERNEL);
210 if (!super)
219 super->reg = reg;
220 super->pllx_index = pllx_index;
221 super->div2_index = div2_index;
222 super->lock = lock;
223 super->width = width;
224 super->flags = clk_super_flags;
227 super->hw.init = &init;
229 clk = clk_register(NULL, &super->hw);
231 kfree(super);
241 struct tegra_clk_super_mux *super;
245 super = kzalloc(sizeof(*super), GFP_KERNEL);
246 if (!super)
255 super->reg = reg;
256 super->lock = lock;
257 super->width = 4;
258 super->flags = clk_super_flags;
259 super->frac_div.reg = reg + 4;
260 super->frac_div.shift = 16;
261 super->frac_div.width = 8;
262 super->frac_div.frac_width = 1;
263 super->frac_div.lock = lock;
264 super->div_ops = &tegra_clk_frac_div_ops;
267 super->hw.init = &init;
269 clk = clk_register(NULL, &super->hw);
271 kfree(super);