Lines Matching refs:pll
276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
286 val = pll_readl_misc(pll);
287 val |= BIT(pll->params->lock_enable_bit_idx);
288 pll_writel_misc(val, pll);
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
298 udelay(pll->params->lock_delay);
302 lock_addr = pll->clk_base;
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
304 lock_addr += pll->params->misc_reg;
306 lock_addr += pll->params->base_reg;
308 lock_mask = pll->params->lock_mask;
310 for (i = 0; i < pll->params->lock_delay; i++) {
319 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
320 clk_hw_get_name(&pll->hw));
325 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
327 return clk_pll_wait_for_lock(pll);
330 static bool pllm_clk_is_gated_by_pmc(struct tegra_clk_pll *pll)
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
340 struct tegra_clk_pll *pll = to_clk_pll(hw);
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll))
351 val = pll_readl_base(pll);
358 struct tegra_clk_pll *pll = to_clk_pll(hw);
361 if (pll->params->iddq_reg) {
362 val = pll_readl(pll->params->iddq_reg, pll);
363 val &= ~BIT(pll->params->iddq_bit_idx);
364 pll_writel(val, pll->params->iddq_reg, pll);
368 if (pll->params->reset_reg) {
369 val = pll_readl(pll->params->reset_reg, pll);
370 val &= ~BIT(pll->params->reset_bit_idx);
371 pll_writel(val, pll->params->reset_reg, pll);
374 clk_pll_enable_lock(pll);
376 val = pll_readl_base(pll);
377 if (pll->params->flags & TEGRA_PLL_BYPASS)
380 pll_writel_base(val, pll);
382 if (pll->params->flags & TEGRA_PLLM) {
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
391 struct tegra_clk_pll *pll = to_clk_pll(hw);
394 val = pll_readl_base(pll);
395 if (pll->params->flags & TEGRA_PLL_BYPASS)
398 pll_writel_base(val, pll);
400 if (pll->params->flags & TEGRA_PLLM) {
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
406 if (pll->params->reset_reg) {
407 val = pll_readl(pll->params->reset_reg, pll);
408 val |= BIT(pll->params->reset_bit_idx);
409 pll_writel(val, pll->params->reset_reg, pll);
412 if (pll->params->iddq_reg) {
413 val = pll_readl(pll->params->iddq_reg, pll);
414 val |= BIT(pll->params->iddq_bit_idx);
415 pll_writel(val, pll->params->iddq_reg, pll);
420 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
425 val |= pll->params->ssc_ctrl_en_mask;
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
430 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
435 val &= ~pll->params->ssc_ctrl_en_mask;
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
442 struct tegra_clk_pll *pll = to_clk_pll(hw);
449 if (pll->lock)
450 spin_lock_irqsave(pll->lock, flags);
454 ret = clk_pll_wait_for_lock(pll);
456 pll_clk_start_ss(pll);
458 if (pll->lock)
459 spin_unlock_irqrestore(pll->lock, flags);
466 struct tegra_clk_pll *pll = to_clk_pll(hw);
469 if (pll->lock)
470 spin_lock_irqsave(pll->lock, flags);
472 pll_clk_stop_ss(pll);
476 if (pll->lock)
477 spin_unlock_irqrestore(pll->lock, flags);
482 struct tegra_clk_pll *pll = to_clk_pll(hw);
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
496 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
498 return _p_div_to_hw(&pll->hw, p_div);
503 struct tegra_clk_pll *pll = to_clk_pll(hw);
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
522 struct tegra_clk_pll *pll = to_clk_pll(hw);
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
534 if (pll->params->pdiv_tohw) {
556 struct tegra_clk_pll *pll = to_clk_pll(hw);
595 if (cfg->m == 0 || cfg->m > divm_max(pll) ||
596 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
597 cfg->output_rate > pll->params->vco_max) {
604 if (pll->params->pdiv_tohw) {
627 struct tegra_clk_pll *pll = to_clk_pll(hw);
631 if (!pll->params->sdm_din_reg)
635 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
636 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
637 pll_writel_sdm_din(val, pll);
640 val = pll_readl_sdm_ctrl(pll);
641 enabled = (val & sdm_en_mask(pll));
644 val &= ~pll->params->sdm_ctrl_en_mask;
647 val |= pll->params->sdm_ctrl_en_mask;
649 pll_writel_sdm_ctrl(val, pll);
652 static void _update_pll_mnp(struct tegra_clk_pll *pll,
656 struct tegra_clk_pll_params *params = pll->params;
660 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
662 val = pll_override_readl(params->pmc_divp_reg, pll);
663 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
665 pll_override_writel(val, params->pmc_divp_reg, pll);
667 val = pll_override_readl(params->pmc_divnm_reg, pll);
668 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
669 (divn_mask(pll) << div_nmp->override_divn_shift));
672 pll_override_writel(val, params->pmc_divnm_reg, pll);
674 val = pll_readl_base(pll);
676 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
677 divp_mask_shifted(pll));
679 val |= (cfg->m << divm_shift(pll)) |
680 (cfg->n << divn_shift(pll)) |
681 (cfg->p << divp_shift(pll));
683 pll_writel_base(val, pll);
685 clk_pll_set_sdm_data(&pll->hw, cfg);
689 static void _get_pll_mnp(struct tegra_clk_pll *pll,
693 struct tegra_clk_pll_params *params = pll->params;
699 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
701 val = pll_override_readl(params->pmc_divp_reg, pll);
702 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
704 val = pll_override_readl(params->pmc_divnm_reg, pll);
705 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
706 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
708 val = pll_readl_base(pll);
710 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
711 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
712 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
714 if (pll->params->sdm_din_reg) {
715 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
716 val = pll_readl_sdm_din(pll);
717 val &= sdm_din_mask(pll);
724 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
730 val = pll_readl_misc(pll);
735 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
739 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
741 if (rate >= (pll->params->vco_max >> 1))
745 pll_writel_misc(val, pll);
751 struct tegra_clk_pll *pll = to_clk_pll(hw);
757 if (state && pll->params->pre_rate_change) {
758 ret = pll->params->pre_rate_change();
763 _get_pll_mnp(pll, &old_cfg);
765 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
767 ret = pll->params->dyn_ramp(pll, cfg);
773 pll_clk_stop_ss(pll);
777 if (!pll->params->defaults_set && pll->params->set_defaults)
778 pll->params->set_defaults(pll);
780 _update_pll_mnp(pll, cfg);
782 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
783 _update_pll_cpcon(pll, cfg, rate);
787 ret = clk_pll_wait_for_lock(pll);
788 pll_clk_start_ss(pll);
792 if (state && pll->params->post_rate_change)
793 pll->params->post_rate_change();
801 struct tegra_clk_pll *pll = to_clk_pll(hw);
806 if (pll->params->flags & TEGRA_PLL_FIXED) {
807 if (rate != pll->params->fixed_rate) {
810 pll->params->fixed_rate, rate);
817 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
823 if (pll->lock)
824 spin_lock_irqsave(pll->lock, flags);
826 _get_pll_mnp(pll, &old_cfg);
827 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
834 if (pll->lock)
835 spin_unlock_irqrestore(pll->lock, flags);
843 struct tegra_clk_pll *pll = to_clk_pll(hw);
846 if (pll->params->flags & TEGRA_PLL_FIXED) {
848 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
850 return pll->params->fixed_rate;
854 pll->params->calc_rate(hw, &cfg, rate, *prate))
863 struct tegra_clk_pll *pll = to_clk_pll(hw);
869 val = pll_readl_base(pll);
871 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
874 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
875 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
878 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
884 return pll->params->fixed_rate;
887 _get_pll_mnp(pll, &cfg);
889 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
900 if (pll->params->set_gain)
901 pll->params->set_gain(&cfg);
911 static int clk_plle_training(struct tegra_clk_pll *pll)
916 if (!pll->pmc)
923 val = readl(pll->pmc + PMC_SATA_PWRGT);
925 writel(val, pll->pmc + PMC_SATA_PWRGT);
927 val = readl(pll->pmc + PMC_SATA_PWRGT);
929 writel(val, pll->pmc + PMC_SATA_PWRGT);
931 val = readl(pll->pmc + PMC_SATA_PWRGT);
933 writel(val, pll->pmc + PMC_SATA_PWRGT);
935 val = pll_readl_misc(pll);
939 val = pll_readl_misc(pll);
954 struct tegra_clk_pll *pll = to_clk_pll(hw);
965 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
970 val = pll_readl_misc(pll);
972 pll_writel_misc(val, pll);
974 val = pll_readl_misc(pll);
976 err = clk_plle_training(pll);
981 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
983 val = pll_readl_base(pll);
984 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
985 divm_mask_shifted(pll));
987 val |= sel.m << divm_shift(pll);
988 val |= sel.n << divn_shift(pll);
989 val |= sel.p << divp_shift(pll);
991 pll_writel_base(val, pll);
994 val = pll_readl_misc(pll);
997 pll_writel_misc(val, pll);
999 val = readl(pll->clk_base + PLLE_SS_CTRL);
1002 writel(val, pll->clk_base + PLLE_SS_CTRL);
1004 val = pll_readl_base(pll);
1006 pll_writel_base(val, pll);
1008 clk_pll_wait_for_lock(pll);
1016 struct tegra_clk_pll *pll = to_clk_pll(hw);
1017 u32 val = pll_readl_base(pll);
1021 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1022 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1023 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1033 struct tegra_clk_pll *pll = to_clk_pll(hw);
1041 if (pll->params->set_defaults)
1042 pll->params->set_defaults(pll);
1115 struct tegra_clk_pll *pll = to_clk_pll(hw);
1131 if (pll->lock)
1132 spin_lock_irqsave(pll->lock, flags);
1137 ret = clk_pll_wait_for_lock(pll);
1155 value = pll_readl_base(pll);
1157 pll_writel_base(value, pll);
1159 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1169 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1171 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1181 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1184 if (pll->lock)
1185 spin_unlock_irqrestore(pll->lock, flags);
1221 struct tegra_clk_pll *pll = to_clk_pll(hw);
1228 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1229 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1240 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1253 struct tegra_clk_pll *pll = to_clk_pll(hw);
1255 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1304 struct tegra_clk_pll *pll = to_clk_pll(hw);
1311 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1318 if (cfg->p > pll->params->max_p)
1328 struct tegra_clk_pll *pll = to_clk_pll(hw);
1337 if (pll->lock)
1338 spin_lock_irqsave(pll->lock, flags);
1340 _get_pll_mnp(pll, &old_cfg);
1341 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1347 if (pll->lock)
1348 spin_unlock_irqrestore(pll->lock, flags);
1356 struct tegra_clk_pll *pll = to_clk_pll(hw);
1369 if (pll->params->set_gain)
1370 pll->params->set_gain(&cfg);
1378 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1382 val = pll_readl_misc(pll);
1384 pll_writel_misc(val, pll);
1388 pll_writel_misc(val, pll);
1393 struct tegra_clk_pll *pll = to_clk_pll(hw);
1401 if (pll->lock)
1402 spin_lock_irqsave(pll->lock, flags);
1407 val = pll_readl_misc(pll);
1409 pll_writel_misc(val, pll);
1412 _pllcx_strobe(pll);
1414 ret = clk_pll_wait_for_lock(pll);
1416 if (pll->lock)
1417 spin_unlock_irqrestore(pll->lock, flags);
1424 struct tegra_clk_pll *pll = to_clk_pll(hw);
1429 val = pll_readl_misc(pll);
1431 pll_writel_misc(val, pll);
1437 struct tegra_clk_pll *pll = to_clk_pll(hw);
1440 if (pll->lock)
1441 spin_lock_irqsave(pll->lock, flags);
1445 if (pll->lock)
1446 spin_unlock_irqrestore(pll->lock, flags);
1449 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1474 val = pll_readl_misc(pll);
1478 pll_writel_misc(val, pll);
1487 struct tegra_clk_pll *pll = to_clk_pll(hw);
1491 if (pll->lock)
1492 spin_lock_irqsave(pll->lock, flags);
1498 _get_pll_mnp(pll, &old_cfg);
1512 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1516 _update_pll_mnp(pll, &cfg);
1522 if (pll->lock)
1523 spin_unlock_irqrestore(pll->lock, flags);
1528 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1535 m = _pll_fixed_mdiv(pll->params, parent_rate);
1553 struct tegra_clk_pll *pll = to_clk_pll(hw);
1557 if (pll->lock)
1558 spin_lock_irqsave(pll->lock, flags);
1560 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1561 _get_pll_mnp(pll, &old_cfg);
1569 _update_pll_mnp(pll, &cfg);
1573 ret = clk_pll_wait_for_lock(pll);
1577 if (pll->lock)
1578 spin_unlock_irqrestore(pll->lock, flags);
1587 struct tegra_clk_pll *pll = to_clk_pll(hw);
1590 _get_pll_mnp(pll, &cfg);
1601 struct tegra_clk_pll *pll = to_clk_pll(hw);
1603 return _pllre_calc_rate(pll, NULL, rate, *prate);
1608 struct tegra_clk_pll *pll = to_clk_pll(hw);
1617 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1620 if (pll->lock)
1621 spin_lock_irqsave(pll->lock, flags);
1623 val = pll_readl_base(pll);
1625 pll_writel_base(val, pll);
1627 val = pll_readl(pll->params->aux_reg, pll);
1630 pll_writel(val, pll->params->aux_reg, pll);
1633 val = pll_readl_misc(pll);
1639 pll_writel_misc(val, pll);
1642 val = pll_readl(PLLE_SS_CTRL, pll);
1644 pll_writel(val, PLLE_SS_CTRL, pll);
1646 val = pll_readl_base(pll);
1647 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1648 divm_mask_shifted(pll));
1650 val |= sel.m << divm_shift(pll);
1651 val |= sel.n << divn_shift(pll);
1653 pll_writel_base(val, pll);
1657 ret = clk_pll_wait_for_lock(pll);
1662 val = pll_readl(PLLE_SS_CTRL, pll);
1666 pll_writel(val, PLLE_SS_CTRL, pll);
1668 pll_writel(val, PLLE_SS_CTRL, pll);
1671 pll_writel(val, PLLE_SS_CTRL, pll);
1675 val = pll_readl_misc(pll);
1677 pll_writel_misc(val, pll);
1679 val = pll_readl(pll->params->aux_reg, pll);
1682 pll_writel(val, pll->params->aux_reg, pll);
1685 pll_writel(val, pll->params->aux_reg, pll);
1687 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1692 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1695 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1698 val = pll_readl(SATA_PLL_CFG0, pll);
1702 pll_writel(val, SATA_PLL_CFG0, pll);
1706 val = pll_readl(SATA_PLL_CFG0, pll);
1708 pll_writel(val, SATA_PLL_CFG0, pll);
1711 if (pll->lock)
1712 spin_unlock_irqrestore(pll->lock, flags);
1719 struct tegra_clk_pll *pll = to_clk_pll(hw);
1723 if (pll->lock)
1724 spin_lock_irqsave(pll->lock, flags);
1728 val = pll_readl_misc(pll);
1730 pll_writel_misc(val, pll);
1733 if (pll->lock)
1734 spin_unlock_irqrestore(pll->lock, flags);
1739 struct tegra_clk_pll *pll = to_clk_pll(hw);
1754 if (pll->lock)
1755 spin_lock_irqsave(pll->lock, flags);
1760 ret = clk_pll_wait_for_lock(pll);
1778 value = pll_readl_base(pll);
1780 pll_writel_base(value, pll);
1782 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1792 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1794 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1805 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1808 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1812 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1814 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1817 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1825 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1828 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1833 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1835 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1838 if (pll->lock)
1839 spin_unlock_irqrestore(pll->lock, flags);
1844 static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)
1849 val = pll_readl_base(pll);
1850 val_aux = pll_readl(pll->params->aux_reg, pll);
1860 pll_writel(val_aux, pll->params->aux_reg, pll);
1861 fence_udelay(1, pll->clk_base);
1870 struct tegra_clk_pll *pll;
1872 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1873 if (!pll)
1876 pll->clk_base = clk_base;
1877 pll->pmc = pmc;
1879 pll->params = pll_params;
1880 pll->lock = lock;
1885 return pll;
1888 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1901 if (!pll->params->calc_rate) {
1902 if (pll->params->flags & TEGRA_PLLM)
1903 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1905 pll->params->calc_rate = _calc_rate;
1908 if (pll->params->set_defaults)
1909 pll->params->set_defaults(pll);
1912 pll->hw.init = &init;
1914 return clk_register(NULL, &pll->hw);
1922 struct tegra_clk_pll *pll;
1927 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1928 if (IS_ERR(pll))
1929 return ERR_CAST(pll);
1931 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1934 kfree(pll);
1953 struct tegra_clk_pll *pll;
1961 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1962 if (IS_ERR(pll))
1963 return ERR_CAST(pll);
1965 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1968 kfree(pll);
1977 struct tegra_clk_pll *pll;
1982 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1983 if (IS_ERR(pll))
1984 return ERR_CAST(pll);
1986 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1989 kfree(pll);
2045 struct tegra_clk_pll *pll;
2069 * If the pll has a set_defaults callback, it will take care of
2091 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2092 if (IS_ERR(pll))
2093 return ERR_CAST(pll);
2095 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2098 kfree(pll);
2110 struct tegra_clk_pll *pll;
2119 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2120 if (IS_ERR(pll))
2121 return ERR_CAST(pll);
2125 val = pll_readl_base(pll);
2133 val = m << divm_shift(pll);
2134 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2135 pll_writel_base(val, pll);
2140 val = pll_readl_misc(pll);
2142 pll_writel_misc(val, pll);
2144 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2147 kfree(pll);
2158 struct tegra_clk_pll *pll;
2182 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2183 if (IS_ERR(pll))
2184 return ERR_CAST(pll);
2186 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2189 kfree(pll);
2202 struct tegra_clk_pll *pll;
2221 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2222 if (IS_ERR(pll))
2223 return ERR_CAST(pll);
2250 pll_writel_base(0, pll);
2251 _update_pll_mnp(pll, &cfg);
2253 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2254 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2255 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2256 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2258 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2260 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2263 kfree(pll);
2274 struct tegra_clk_pll *pll;
2277 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2278 if (IS_ERR(pll))
2279 return ERR_CAST(pll);
2281 _clk_plle_tegra_init_parent(pll);
2283 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2286 kfree(pll);
2297 struct tegra_clk_pll *pll;
2302 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2303 if (IS_ERR(pll))
2304 return ERR_CAST(pll);
2306 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2309 kfree(pll);
2331 struct tegra_clk_pll *pll;
2348 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2349 if (IS_ERR(pll))
2350 return ERR_CAST(pll);
2352 val = pll_readl_base(pll);
2354 pll_writel_base(val, pll);
2368 kfree(pll);
2374 _update_pll_mnp(pll, &cfg);
2376 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2377 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2378 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2379 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2381 val = pll_readl_base(pll);
2386 kfree(pll);
2395 pll_writel_base(val, pll);
2397 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2401 kfree(pll);
2414 struct tegra_clk_pll *pll;
2423 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2424 if (IS_ERR(pll))
2425 return ERR_CAST(pll);
2427 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2430 kfree(pll);
2437 struct tegra_clk_pll *pll = to_clk_pll(hw);
2440 val = pll_readl_base(pll);
2447 struct tegra_clk_pll *pll = to_clk_pll(hw);
2459 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2462 if (pll->lock)
2463 spin_lock_irqsave(pll->lock, flags);
2465 val = pll_readl(pll->params->aux_reg, pll);
2469 val = pll_readl_base(pll);
2471 pll_writel_base(val, pll);
2473 val = pll_readl_misc(pll);
2479 pll_writel_misc(val, pll);
2482 val = pll_readl(PLLE_SS_CTRL, pll);
2484 pll_writel(val, PLLE_SS_CTRL, pll);
2486 val = pll_readl_base(pll);
2487 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2488 divm_mask_shifted(pll));
2490 val |= sel.m << divm_shift(pll);
2491 val |= sel.n << divn_shift(pll);
2493 pll_writel_base(val, pll);
2496 val = pll_readl_base(pll);
2498 pll_writel_base(val, pll);
2500 ret = clk_pll_wait_for_lock(pll);
2505 val = pll_readl(PLLE_SS_CTRL, pll);
2509 pll_writel(val, PLLE_SS_CTRL, pll);
2511 pll_writel(val, PLLE_SS_CTRL, pll);
2514 pll_writel(val, PLLE_SS_CTRL, pll);
2517 val = pll_readl_misc(pll);
2519 pll_writel_misc(val, pll);
2521 val = pll_readl(pll->params->aux_reg, pll);
2524 pll_writel(val, pll->params->aux_reg, pll);
2527 pll_writel(val, pll->params->aux_reg, pll);
2530 if (pll->lock)
2531 spin_unlock_irqrestore(pll->lock, flags);
2538 struct tegra_clk_pll *pll = to_clk_pll(hw);
2542 if (pll->lock)
2543 spin_lock_irqsave(pll->lock, flags);
2546 val = pll_readl(pll->params->aux_reg, pll);
2550 val = pll_readl_base(pll);
2552 pll_writel_base(val, pll);
2554 val = pll_readl(pll->params->aux_reg, pll);
2556 pll_writel(val, pll->params->aux_reg, pll);
2558 val = pll_readl_misc(pll);
2560 pll_writel_misc(val, pll);
2564 if (pll->lock)
2565 spin_unlock_irqrestore(pll->lock, flags);
2570 struct tegra_clk_pll *pll = to_clk_pll(hw);
2572 _clk_plle_tegra_init_parent(pll);
2589 struct tegra_clk_pll *pll;
2592 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2593 if (IS_ERR(pll))
2594 return ERR_CAST(pll);
2596 _clk_plle_tegra_init_parent(pll);
2598 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2601 kfree(pll);
2614 struct tegra_clk_pll *pll;
2636 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2637 if (IS_ERR(pll))
2638 return ERR_CAST(pll);
2640 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2643 kfree(pll);
2654 struct tegra_clk_pll *pll;
2684 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2685 if (IS_ERR(pll))
2686 return ERR_CAST(pll);
2688 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2692 kfree(pll);
2703 struct tegra_clk_pll *pll;
2727 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2728 if (IS_ERR(pll))
2729 return ERR_CAST(pll);
2731 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2734 kfree(pll);