Lines Matching defs:val
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
278 u32 val;
286 val = pll_readl_misc(pll);
287 val |= BIT(pll->params->lock_enable_bit_idx);
288 pll_writel_misc(val, pll);
294 u32 val, lock_mask;
311 val = readl_relaxed(lock_addr);
312 if ((val & lock_mask) == lock_mask) {
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
334 return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
335 !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
341 u32 val;
351 val = pll_readl_base(pll);
353 return val & PLL_BASE_ENABLE ? 1 : 0;
359 u32 val;
362 val = pll_readl(pll->params->iddq_reg, pll);
363 val &= ~BIT(pll->params->iddq_bit_idx);
364 pll_writel(val, pll->params->iddq_reg, pll);
369 val = pll_readl(pll->params->reset_reg, pll);
370 val &= ~BIT(pll->params->reset_bit_idx);
371 pll_writel(val, pll->params->reset_reg, pll);
376 val = pll_readl_base(pll);
378 val &= ~PLL_BASE_BYPASS;
379 val |= PLL_BASE_ENABLE;
380 pll_writel_base(val, pll);
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
384 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
392 u32 val;
394 val = pll_readl_base(pll);
396 val &= ~PLL_BASE_BYPASS;
397 val &= ~PLL_BASE_ENABLE;
398 pll_writel_base(val, pll);
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
402 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
407 val = pll_readl(pll->params->reset_reg, pll);
408 val |= BIT(pll->params->reset_bit_idx);
409 pll_writel(val, pll->params->reset_reg, pll);
413 val = pll_readl(pll->params->iddq_reg, pll);
414 val |= BIT(pll->params->iddq_bit_idx);
415 pll_writel(val, pll->params->iddq_reg, pll);
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
425 val |= pll->params->ssc_ctrl_en_mask;
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
435 val &= ~pll->params->ssc_ctrl_en_mask;
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
628 u32 val;
635 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
636 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
637 pll_writel_sdm_din(val, pll);
640 val = pll_readl_sdm_ctrl(pll);
641 enabled = (val & sdm_en_mask(pll));
644 val &= ~pll->params->sdm_ctrl_en_mask;
647 val |= pll->params->sdm_ctrl_en_mask;
649 pll_writel_sdm_ctrl(val, pll);
655 u32 val;
662 val = pll_override_readl(params->pmc_divp_reg, pll);
663 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
664 val |= cfg->p << div_nmp->override_divp_shift;
665 pll_override_writel(val, params->pmc_divp_reg, pll);
667 val = pll_override_readl(params->pmc_divnm_reg, pll);
668 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
670 val |= (cfg->m << div_nmp->override_divm_shift) |
672 pll_override_writel(val, params->pmc_divnm_reg, pll);
674 val = pll_readl_base(pll);
676 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
679 val |= (cfg->m << divm_shift(pll)) |
683 pll_writel_base(val, pll);
692 u32 val;
701 val = pll_override_readl(params->pmc_divp_reg, pll);
702 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
704 val = pll_override_readl(params->pmc_divnm_reg, pll);
705 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
706 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
708 val = pll_readl_base(pll);
710 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
711 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
712 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
716 val = pll_readl_sdm_din(pll);
717 val &= sdm_din_mask(pll);
718 cfg->sdm_data = sdin_din_to_data(val);
728 u32 val;
730 val = pll_readl_misc(pll);
732 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
733 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
736 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
738 val |= 1 << PLL_MISC_LFCON_SHIFT;
740 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
742 val |= 1 << PLL_MISC_DCCON_SHIFT;
745 pll_writel_misc(val, pll);
865 u32 val;
869 val = pll_readl_base(pll);
871 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
876 !(val & PLL_BASE_OVERRIDE)) {
913 u32 val;
923 val = readl(pll->pmc + PMC_SATA_PWRGT);
924 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
925 writel(val, pll->pmc + PMC_SATA_PWRGT);
927 val = readl(pll->pmc + PMC_SATA_PWRGT);
928 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
929 writel(val, pll->pmc + PMC_SATA_PWRGT);
931 val = readl(pll->pmc + PMC_SATA_PWRGT);
932 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
933 writel(val, pll->pmc + PMC_SATA_PWRGT);
935 val = pll_readl_misc(pll);
939 val = pll_readl_misc(pll);
940 if (val & PLLE_MISC_READY)
957 u32 val;
970 val = pll_readl_misc(pll);
971 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
972 pll_writel_misc(val, pll);
974 val = pll_readl_misc(pll);
975 if (!(val & PLLE_MISC_READY)) {
983 val = pll_readl_base(pll);
984 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
986 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
987 val |= sel.m << divm_shift(pll);
988 val |= sel.n << divn_shift(pll);
989 val |= sel.p << divp_shift(pll);
990 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
991 pll_writel_base(val, pll);
994 val = pll_readl_misc(pll);
995 val |= PLLE_MISC_SETUP_VALUE;
996 val |= PLLE_MISC_LOCK_ENABLE;
997 pll_writel_misc(val, pll);
999 val = readl(pll->clk_base + PLLE_SS_CTRL);
1000 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1001 val |= PLLE_SS_DISABLE;
1002 writel(val, pll->clk_base + PLLE_SS_CTRL);
1004 val = pll_readl_base(pll);
1005 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1006 pll_writel_base(val, pll);
1017 u32 val = pll_readl_base(pll);
1021 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1022 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1023 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1268 u32 val;
1293 val = step_a << pll_params->stepa_shift;
1294 val |= step_b << pll_params->stepb_shift;
1295 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1380 u32 val;
1382 val = pll_readl_misc(pll);
1383 val |= PLLCX_MISC_STROBE;
1384 pll_writel_misc(val, pll);
1387 val &= ~PLLCX_MISC_STROBE;
1388 pll_writel_misc(val, pll);
1394 u32 val;
1407 val = pll_readl_misc(pll);
1408 val &= ~PLLCX_MISC_RESET;
1409 pll_writel_misc(val, pll);
1425 u32 val;
1429 val = pll_readl_misc(pll);
1430 val |= PLLCX_MISC_RESET;
1431 pll_writel_misc(val, pll);
1452 u32 val, n_threshold;
1474 val = pll_readl_misc(pll);
1475 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1476 val |= n <= n_threshold ?
1478 pll_writel_misc(val, pll);
1610 u32 val;
1623 val = pll_readl_base(pll);
1624 val &= ~BIT(29); /* Disable lock override */
1625 pll_writel_base(val, pll);
1627 val = pll_readl(pll->params->aux_reg, pll);
1628 val |= PLLE_AUX_ENABLE_SWCTL;
1629 val &= ~PLLE_AUX_SEQ_ENABLE;
1630 pll_writel(val, pll->params->aux_reg, pll);
1633 val = pll_readl_misc(pll);
1634 val |= PLLE_MISC_LOCK_ENABLE;
1635 val |= PLLE_MISC_IDDQ_SW_CTRL;
1636 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1637 val |= PLLE_MISC_PLLE_PTS;
1638 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1639 pll_writel_misc(val, pll);
1642 val = pll_readl(PLLE_SS_CTRL, pll);
1643 val |= PLLE_SS_DISABLE;
1644 pll_writel(val, PLLE_SS_CTRL, pll);
1646 val = pll_readl_base(pll);
1647 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1649 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1650 val |= sel.m << divm_shift(pll);
1651 val |= sel.n << divn_shift(pll);
1652 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1653 pll_writel_base(val, pll);
1662 val = pll_readl(PLLE_SS_CTRL, pll);
1663 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1664 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1665 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1666 pll_writel(val, PLLE_SS_CTRL, pll);
1667 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1668 pll_writel(val, PLLE_SS_CTRL, pll);
1670 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1671 pll_writel(val, PLLE_SS_CTRL, pll);
1675 val = pll_readl_misc(pll);
1676 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1677 pll_writel_misc(val, pll);
1679 val = pll_readl(pll->params->aux_reg, pll);
1680 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1681 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1682 pll_writel(val, pll->params->aux_reg, pll);
1684 val |= PLLE_AUX_SEQ_ENABLE;
1685 pll_writel(val, pll->params->aux_reg, pll);
1687 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1688 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1690 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1692 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1694 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1695 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1698 val = pll_readl(SATA_PLL_CFG0, pll);
1699 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1700 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1701 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1702 pll_writel(val, SATA_PLL_CFG0, pll);
1706 val = pll_readl(SATA_PLL_CFG0, pll);
1707 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1708 pll_writel(val, SATA_PLL_CFG0, pll);
1721 u32 val;
1728 val = pll_readl_misc(pll);
1729 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1730 pll_writel_misc(val, pll);
1846 u32 val, val_aux;
1849 val = pll_readl_base(pll);
1852 if (val & PLL_BASE_ENABLE) {
2048 u32 val, val_iddq;
2079 val = readl_relaxed(clk_base + pll_params->base_reg);
2082 if (val & PLL_BASE_ENABLE)
2109 u32 val;
2125 val = pll_readl_base(pll);
2126 if (val & PLL_BASE_ENABLE)
2133 val = m << divm_shift(pll);
2134 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2135 pll_writel_base(val, pll);
2140 val = pll_readl_misc(pll);
2141 val &= ~BIT(29);
2142 pll_writel_misc(val, pll);
2335 u32 val, val_iddq;
2352 val = pll_readl_base(pll);
2353 val &= ~PLLSS_REF_SRC_SEL_MASK;
2354 pll_writel_base(val, pll);
2381 val = pll_readl_base(pll);
2383 if (val & PLL_BASE_ENABLE) {
2394 val &= ~PLLSS_LOCK_OVERRIDE;
2395 pll_writel_base(val, pll);
2438 u32 val;
2440 val = pll_readl_base(pll);
2442 return val & PLLE_BASE_ENABLE ? 1 : 0;
2449 u32 val;
2465 val = pll_readl(pll->params->aux_reg, pll);
2466 if (val & PLLE_AUX_SEQ_ENABLE)
2469 val = pll_readl_base(pll);
2470 val &= ~BIT(30); /* Disable lock override */
2471 pll_writel_base(val, pll);
2473 val = pll_readl_misc(pll);
2474 val |= PLLE_MISC_LOCK_ENABLE;
2475 val |= PLLE_MISC_IDDQ_SW_CTRL;
2476 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2477 val |= PLLE_MISC_PLLE_PTS;
2478 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2479 pll_writel_misc(val, pll);
2482 val = pll_readl(PLLE_SS_CTRL, pll);
2483 val |= PLLE_SS_DISABLE;
2484 pll_writel(val, PLLE_SS_CTRL, pll);
2486 val = pll_readl_base(pll);
2487 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2489 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2490 val |= sel.m << divm_shift(pll);
2491 val |= sel.n << divn_shift(pll);
2492 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2493 pll_writel_base(val, pll);
2496 val = pll_readl_base(pll);
2497 val |= PLLE_BASE_ENABLE;
2498 pll_writel_base(val, pll);
2505 val = pll_readl(PLLE_SS_CTRL, pll);
2506 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2507 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2508 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2509 pll_writel(val, PLLE_SS_CTRL, pll);
2510 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2511 pll_writel(val, PLLE_SS_CTRL, pll);
2513 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2514 pll_writel(val, PLLE_SS_CTRL, pll);
2517 val = pll_readl_misc(pll);
2518 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2519 pll_writel_misc(val, pll);
2521 val = pll_readl(pll->params->aux_reg, pll);
2522 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2523 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2524 pll_writel(val, pll->params->aux_reg, pll);
2526 val |= PLLE_AUX_SEQ_ENABLE;
2527 pll_writel(val, pll->params->aux_reg, pll);
2540 u32 val;
2546 val = pll_readl(pll->params->aux_reg, pll);
2547 if (val & PLLE_AUX_SEQ_ENABLE)
2550 val = pll_readl_base(pll);
2551 val &= ~PLLE_BASE_ENABLE;
2552 pll_writel_base(val, pll);
2554 val = pll_readl(pll->params->aux_reg, pll);
2555 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2556 pll_writel(val, pll->params->aux_reg, pll);
2558 val = pll_readl_misc(pll);
2559 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2560 pll_writel_misc(val, pll);
2657 u32 val;
2669 val = readl_relaxed(clk_base + pll_params->base_reg);
2670 if (val & PLLSS_REF_SRC_SEL_MASK) {