Lines Matching defs:ret
444 int ret;
454 ret = clk_pll_wait_for_lock(pll);
461 return ret;
559 int ret;
605 ret = _p_div_to_hw(hw, 1 << p_div);
606 if (ret < 0)
607 return ret;
609 cfg->p = ret;
753 int state, ret = 0;
758 ret = pll->params->pre_rate_change();
759 if (WARN_ON(ret))
760 return ret;
767 ret = pll->params->dyn_ramp(pll, cfg);
768 if (!ret)
787 ret = clk_pll_wait_for_lock(pll);
795 return ret;
804 int ret = 0;
832 ret = _program_pll(hw, &cfg, rate);
837 return ret;
1121 int ret = 0;
1137 ret = clk_pll_wait_for_lock(pll);
1138 if (ret < 0)
1151 ret = -EINVAL;
1187 return ret;
1331 int ret;
1333 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1334 if (ret < 0)
1335 return ret;
1345 ret = _program_pll(hw, &cfg, rate);
1350 return ret;
1358 int ret, p_div;
1361 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1362 if (ret < 0)
1363 return ret;
1395 int ret;
1414 ret = clk_pll_wait_for_lock(pll);
1419 return ret;
1489 int state, ret = 0;
1494 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1495 if (ret < 0)
1512 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1513 if (ret < 0)
1519 ret = clk_pllc_enable(hw);
1525 return ret;
1555 int state, ret = 0;
1573 ret = clk_pll_wait_for_lock(pll);
1580 return ret;
1611 int ret;
1657 ret = clk_pll_wait_for_lock(pll);
1659 if (ret < 0)
1714 return ret;
1744 int ret = 0;
1760 ret = clk_pll_wait_for_lock(pll);
1761 if (ret < 0)
1774 ret = -EINVAL;
1841 return ret;
2450 int ret = 0;
2500 ret = clk_pll_wait_for_lock(pll);
2502 if (ret < 0)
2533 return ret;