Lines Matching defs:pll_params
1199 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1202 u16 mdiv = parent_rate / pll_params->cf_min;
1204 if (pll_params->flags & TEGRA_MDIV_NEW)
1205 return (!pll_params->mdiv_default ? mdiv :
1206 min(mdiv, pll_params->mdiv_default));
1208 if (pll_params->mdiv_default)
1209 return pll_params->mdiv_default;
1211 if (parent_rate > pll_params->cf_max)
1264 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1293 val = step_a << pll_params->stepa_shift;
1294 val |= step_b << pll_params->stepb_shift;
1295 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1867 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1879 pll->params = pll_params;
1882 if (!pll_params->div_nmp)
1883 pll_params->div_nmp = &default_nmp;
1919 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1925 pll_params->flags |= TEGRA_PLL_BYPASS;
1927 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1950 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1956 pll_params->flags |= TEGRA_PLL_BYPASS;
1958 if (!pll_params->div_nmp)
1959 pll_params->div_nmp = &pll_e_nmp;
1961 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1975 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1980 pll_params->flags |= TEGRA_PLLU;
1982 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2042 struct tegra_clk_pll_params *pll_params,
2057 if (!pll_params->pdiv_tohw)
2062 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2064 if (pll_params->adjust_vco)
2065 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2072 if (!pll_params->set_defaults) {
2075 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2079 val = readl_relaxed(clk_base + pll_params->base_reg);
2080 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2083 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2085 val_iddq |= BIT(pll_params->iddq_bit_idx);
2087 clk_base + pll_params->iddq_reg);
2091 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2106 struct tegra_clk_pll_params *pll_params,
2113 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2115 if (pll_params->adjust_vco)
2116 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2119 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2127 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2128 BIT(pll_params->iddq_bit_idx));
2132 m = _pll_fixed_mdiv(pll_params, parent_rate);
2134 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2155 struct tegra_clk_pll_params *pll_params,
2162 if (!pll_params->pdiv_tohw)
2174 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2176 if (pll_params->adjust_vco)
2177 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2180 pll_params->flags |= TEGRA_PLL_BYPASS;
2181 pll_params->flags |= TEGRA_PLLM;
2182 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2197 struct tegra_clk_pll_params *pll_params,
2201 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2218 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2220 pll_params->flags |= TEGRA_PLL_BYPASS;
2221 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2234 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2235 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2254 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2255 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2256 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2271 struct tegra_clk_pll_params *pll_params,
2277 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2294 struct tegra_clk_pll_params *pll_params,
2300 pll_params->flags |= TEGRA_PLLU;
2302 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2328 struct tegra_clk_pll_params *pll_params,
2338 if (!pll_params->div_nmp)
2348 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2358 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2362 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2363 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2365 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2372 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2377 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2378 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2379 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2382 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2384 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2390 val_iddq |= BIT(pll_params->iddq_bit_idx);
2391 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2411 struct tegra_clk_pll_params *pll_params,
2417 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2419 if (pll_params->adjust_vco)
2420 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2423 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2586 struct tegra_clk_pll_params *pll_params,
2592 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2609 struct tegra_clk_pll_params *pll_params,
2613 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2629 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2631 if (pll_params->adjust_vco)
2632 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2635 pll_params->flags |= TEGRA_PLL_BYPASS;
2636 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2651 struct tegra_clk_pll_params *pll_params,
2659 if (!pll_params->div_nmp)
2669 val = readl_relaxed(clk_base + pll_params->base_reg);
2677 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2679 if (pll_params->adjust_vco)
2680 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2683 pll_params->flags |= TEGRA_PLL_BYPASS;
2684 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2700 struct tegra_clk_pll_params *pll_params,
2707 if (!pll_params->pdiv_tohw)
2719 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2721 if (pll_params->adjust_vco)
2722 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2725 pll_params->flags |= TEGRA_PLL_BYPASS;
2726 pll_params->flags |= TEGRA_PLLMB;
2727 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);