Lines Matching defs:input_rate
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
527 if (sel->input_rate == parent_rate &&
531 if (sel->input_rate == 0)
542 cfg->input_rate = sel->input_rate;
956 unsigned long input_rate;
963 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
965 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1119 unsigned long flags = 0, input_rate;
1129 input_rate = clk_hw_get_rate(osc);
1142 if (input_rate == utmi_parameters[i].osc_frequency) {
1150 input_rate);
1232 cfg->input_rate = parent_rate;
1251 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1255 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1450 unsigned long input_rate, u32 n)
1454 switch (input_rate) {
1470 __func__, input_rate);
1613 unsigned long input_rate;
1615 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1617 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1742 unsigned long flags = 0, input_rate;
1752 input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1765 if (input_rate == utmi_parameters[i].osc_frequency) {
1773 input_rate);
2452 unsigned long input_rate;
2457 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2459 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))