clk-pll.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/clk/tegra/clk-pll.c

Lines Matching defs:clk_base
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
302 	lock_addr = pll->clk_base;
999 	val = readl(pll->clk_base + PLLE_SS_CTRL);
1002 	writel(val, pll->clk_base + PLLE_SS_CTRL);
1159 	value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1169 	writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1171 	value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1181 	writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1265 			       void __iomem *clk_base,
1295 	writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1782 	value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1792 	writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1794 	value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1805 	writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1808 	value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1812 	writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1814 	value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1817 	writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1825 	value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1828 	writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1833 	value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1835 	writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1861 		fence_udelay(1, pll->clk_base);
1866 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1876 	pll->clk_base = clk_base;
1918 		void __iomem *clk_base, void __iomem *pmc,
1927 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1949 		void __iomem *clk_base, void __iomem *pmc,
1961 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1974 		void __iomem *clk_base, unsigned long flags,
1982 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2040 			  void __iomem *clk_base, void __iomem *pmc,
2075 		err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2079 		val = readl_relaxed(clk_base + pll_params->base_reg);
2080 		val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2087 				       clk_base + pll_params->iddq_reg);
2091 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2104 			  void __iomem *clk_base, void __iomem *pmc,
2119 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2127 		WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2153 			  void __iomem *clk_base, void __iomem *pmc,
2182 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2195 			  void __iomem *clk_base, void __iomem *pmc,
2221 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2270 				void __iomem *clk_base, unsigned long flags,
2277 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2293 				 void __iomem *clk_base, unsigned long flags,
2302 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2327 				void __iomem *clk_base, unsigned long flags,
2348 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2382 	val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2391 		writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2409 			  const char *parent_name, void __iomem *clk_base,
2423 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2585 				void __iomem *clk_base, unsigned long flags,
2592 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2607 			const char *parent_name, void __iomem *clk_base,
2636 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2649 				const char *parent_name, void __iomem *clk_base,
2669 	val = readl_relaxed(clk_base + pll_params->base_reg);
2684 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2698 			  void __iomem *clk_base, void __iomem *pmc,
2727 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);