Lines Matching defs:val
86 u32 val;
95 val = readl_relaxed(divider->reg);
96 val &= ~(div_mask(divider) << divider->shift);
97 val |= div << divider->shift;
101 val |= PERIPH_CLK_UART_DIV_ENB;
103 val &= ~PERIPH_CLK_UART_DIV_ENB;
107 val |= pll_out_override(divider);
109 writel_relaxed(val, divider->reg);
174 { .val = 0, .div = 2 },
175 { .val = 1, .div = 1 },
176 { .val = 0, .div = 0 },