Lines Matching refs:td
171 * Integrated I2C controller registers - relative to td->i2c_controller_base
330 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs)
332 return __raw_readl(td->base + offs);
335 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs)
338 __raw_writel(val, td->base + offs);
341 static inline void dfll_wmb(struct tegra_dfll *td)
343 dfll_readl(td, DFLL_CTRL);
348 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs)
350 return __raw_readl(td->i2c_base + offs);
353 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs)
355 __raw_writel(val, td->i2c_base + offs);
358 static inline void dfll_i2c_wmb(struct tegra_dfll *td)
360 dfll_i2c_readl(td, DFLL_I2C_CFG);
365 * @td: DFLL instance
370 static bool dfll_is_running(struct tegra_dfll *td)
372 return td->mode >= DFLL_OPEN_LOOP;
390 struct tegra_dfll *td = dev_get_drvdata(dev);
393 ret = clk_enable(td->ref_clk);
399 ret = clk_enable(td->soc_clk);
402 clk_disable(td->ref_clk);
406 ret = clk_enable(td->i2c_clk);
409 clk_disable(td->soc_clk);
410 clk_disable(td->ref_clk);
427 struct tegra_dfll *td = dev_get_drvdata(dev);
429 clk_disable(td->ref_clk);
430 clk_disable(td->soc_clk);
431 clk_disable(td->i2c_clk);
443 * @td: DFLL instance
449 static void dfll_tune_low(struct tegra_dfll *td)
451 td->tune_range = DFLL_TUNE_LOW;
453 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0);
454 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1);
455 dfll_wmb(td);
457 if (td->soc->set_clock_trimmers_low)
458 td->soc->set_clock_trimmers_low();
485 * @td: DFLL instance
491 static void dfll_set_mode(struct tegra_dfll *td,
494 td->mode = mode;
495 dfll_writel(td, mode - 1, DFLL_CTRL);
496 dfll_wmb(td);
503 static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min)
509 min_uv = td->lut_uv[out_min];
511 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
533 * @td: DFLL instance
539 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable)
543 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG);
550 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);
551 dfll_i2c_wmb(td);
563 * @td: DFLL instance
570 static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable)
576 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state);
578 dev_err(td->dev, "setting enable state failed\n");
581 val = dfll_readl(td, DFLL_OUTPUT_CFG);
583 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate);
586 dfll_writel(td, val, DFLL_OUTPUT_CFG);
587 dfll_wmb(td);
590 dfll_writel(td, val, DFLL_OUTPUT_CFG);
591 dfll_wmb(td);
593 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state);
595 dev_warn(td->dev, "setting disable state failed\n");
597 val = dfll_readl(td, DFLL_OUTPUT_CFG);
599 dfll_writel(td, val, DFLL_OUTPUT_CFG);
600 dfll_wmb(td);
608 * @td: DFLL instance
614 static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val)
616 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
619 dfll_writel(td, val, DFLL_OUTPUT_FORCE);
620 dfll_wmb(td);
622 return dfll_readl(td, DFLL_OUTPUT_FORCE);
627 * @td: DFLL instance
632 static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable)
634 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
641 dfll_writel(td, val, DFLL_OUTPUT_FORCE);
642 dfll_wmb(td);
647 * @td: DFLL instance
652 static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel)
659 val = dfll_set_force_output_value(td, out_sel);
660 if ((td->mode < DFLL_CLOSED_LOOP) &&
662 dfll_set_force_output_enabled(td, true);
670 * @td: struct tegra_dfll *
675 static void dfll_load_i2c_lut(struct tegra_dfll *td)
681 if (i < td->lut_min)
682 lut_index = td->lut_min;
683 else if (i > td->lut_max)
684 lut_index = td->lut_max;
688 val = regulator_list_hardware_vsel(td->vdd_reg,
689 td->lut[lut_index]);
690 __raw_writel(val, td->lut_base + i * 4);
693 dfll_i2c_wmb(td);
698 * @td: DFLL instance
706 static void dfll_init_i2c_if(struct tegra_dfll *td)
710 if (td->i2c_slave_addr > 0x7f) {
711 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT;
714 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT;
718 dfll_i2c_writel(td, val, DFLL_I2C_CFG);
720 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR);
722 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8);
728 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR);
729 dfll_i2c_wmb(td);
734 * @td: DFLL instance
740 static void dfll_init_out_if(struct tegra_dfll *td)
744 td->lut_min = td->lut_bottom;
745 td->lut_max = td->lut_size - 1;
746 td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0);
749 dfll_writel(td, 0, DFLL_OUTPUT_CFG);
750 dfll_wmb(td);
752 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) |
753 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |
754 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);
755 dfll_writel(td, val, DFLL_OUTPUT_CFG);
756 dfll_wmb(td);
758 dfll_writel(td, 0, DFLL_OUTPUT_FORCE);
759 dfll_i2c_writel(td, 0, DFLL_INTR_EN);
760 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK,
763 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) {
764 u32 vinit = td->reg_init_uV;
765 int vstep = td->soc->alignment.step_uv;
766 unsigned long vmin = td->lut_uv[0];
773 dfll_force_output(td, vsel);
776 dfll_load_i2c_lut(td);
777 dfll_init_i2c_if(td);
787 * @td: DFLL instance
795 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
800 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
804 align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;
807 for (i = td->lut_bottom; i < td->lut_size; i++) {
808 if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step)
817 * @td: DFLL instance
826 static int dfll_calculate_rate_request(struct tegra_dfll *td,
839 if (rate < td->dvco_rate_min) {
843 td->dvco_rate_min / 1000);
845 dev_err(td->dev, "%s: Rate %lu is too low\n",
850 rate = td->dvco_rate_min;
854 val = DVCO_RATE_TO_MULT(rate, td->ref_rate);
856 dev_err(td->dev, "%s: Rate %lu is above dfll range\n",
861 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate);
864 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate);
873 * @td: DFLL instance
879 static void dfll_set_frequency_request(struct tegra_dfll *td,
884 int coef = 128; /* FIXME: td->cg_scale? */;
886 force_val = (req->lut_index - td->lut_safe) * coef / td->cg;
895 dfll_writel(td, val, DFLL_FREQ_REQ);
896 dfll_wmb(td);
901 * @td: DFLL instance
911 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate)
916 if (td->mode == DFLL_UNINITIALIZED) {
917 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",
918 __func__, mode_name[td->mode]);
922 ret = dfll_calculate_rate_request(td, &req, rate);
926 td->last_unrounded_rate = rate;
927 td->last_req = req;
929 if (td->mode == DFLL_CLOSED_LOOP)
930 dfll_set_frequency_request(td, &td->last_req);
941 * @td: DFLL instance
946 static int dfll_disable(struct tegra_dfll *td)
948 if (td->mode != DFLL_OPEN_LOOP) {
949 dev_err(td->dev, "cannot disable DFLL in %s mode\n",
950 mode_name[td->mode]);
954 dfll_set_mode(td, DFLL_DISABLED);
955 pm_runtime_put_sync(td->dev);
962 * @td: DFLL instance
967 static int dfll_enable(struct tegra_dfll *td)
969 if (td->mode != DFLL_DISABLED) {
970 dev_err(td->dev, "cannot enable DFLL in %s mode\n",
971 mode_name[td->mode]);
975 pm_runtime_get_sync(td->dev);
976 dfll_set_mode(td, DFLL_OPEN_LOOP);
983 * @td: DFLL instance
992 static void dfll_set_open_loop_config(struct tegra_dfll *td)
997 if (td->tune_range != DFLL_TUNE_LOW)
998 dfll_tune_low(td);
1000 val = dfll_readl(td, DFLL_FREQ_REQ);
1003 dfll_writel(td, val, DFLL_FREQ_REQ);
1004 dfll_wmb(td);
1009 * @td: DFLL instance
1015 static int dfll_lock(struct tegra_dfll *td)
1017 struct dfll_rate_req *req = &td->last_req;
1019 switch (td->mode) {
1025 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",
1030 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1031 dfll_pwm_set_output_enabled(td, true);
1033 dfll_i2c_set_output_enabled(td, true);
1035 dfll_set_mode(td, DFLL_CLOSED_LOOP);
1036 dfll_set_frequency_request(td, req);
1037 dfll_set_force_output_enabled(td, false);
1041 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
1042 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n",
1043 __func__, mode_name[td->mode]);
1050 * @td: DFLL instance
1055 static int dfll_unlock(struct tegra_dfll *td)
1057 switch (td->mode) {
1059 dfll_set_open_loop_config(td);
1060 dfll_set_mode(td, DFLL_OPEN_LOOP);
1061 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1062 dfll_pwm_set_output_enabled(td, false);
1064 dfll_i2c_set_output_enabled(td, false);
1071 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
1072 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n",
1073 __func__, mode_name[td->mode]);
1089 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1091 return dfll_is_running(td);
1096 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1099 ret = dfll_enable(td);
1103 ret = dfll_lock(td);
1105 dfll_disable(td);
1112 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1115 ret = dfll_unlock(td);
1117 dfll_disable(td);
1123 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1125 return td->last_unrounded_rate;
1132 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1136 ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
1152 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1154 return dfll_request_rate(td, rate);
1173 * @td: DFLL instance
1179 static int dfll_register_clk(struct tegra_dfll *td)
1183 dfll_clk_init_data.name = td->output_clock_name;
1184 td->dfll_clk_hw.init = &dfll_clk_init_data;
1186 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw);
1187 if (IS_ERR(td->dfll_clk)) {
1188 dev_err(td->dev, "DFLL clock registration error\n");
1192 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get,
1193 td->dfll_clk);
1195 dev_err(td->dev, "of_clk_add_provider() failed\n");
1197 clk_unregister(td->dfll_clk);
1206 * @td: DFLL instance
1211 static void dfll_unregister_clk(struct tegra_dfll *td)
1213 of_clk_del_provider(td->dev->of_node);
1214 clk_unregister(td->dfll_clk);
1215 td->dfll_clk = NULL;
1243 * @td: DFLL instance
1254 static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
1259 if (!dfll_is_running(td))
1262 v = dfll_readl(td, DFLL_MONITOR_DATA);
1264 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
1266 s = dfll_readl(td, DFLL_FREQ_REQ);
1275 struct tegra_dfll *td = data;
1277 *val = dfll_is_running(td);
1283 struct tegra_dfll *td = data;
1285 return val ? dfll_enable(td) : dfll_disable(td);
1292 struct tegra_dfll *td = data;
1294 *val = (td->mode == DFLL_CLOSED_LOOP);
1300 struct tegra_dfll *td = data;
1302 return val ? dfll_lock(td) : dfll_unlock(td);
1308 struct tegra_dfll *td = data;
1310 *val = dfll_read_monitor_rate(td);
1317 struct tegra_dfll *td = data;
1319 return dfll_request_rate(td, val);
1326 struct tegra_dfll *td = s->private;
1331 val = dfll_i2c_readl(td, offs);
1333 val = dfll_readl(td, offs);
1340 dfll_i2c_readl(td, offs));
1343 dfll_i2c_readl(td, offs));
1345 if (td->pmu_if == TEGRA_DFLL_PMU_I2C) {
1349 __raw_readl(td->i2c_controller_base + offs));
1354 __raw_readl(td->lut_base + offs));
1362 static void dfll_debug_init(struct tegra_dfll *td)
1366 if (!td || (td->mode == DFLL_UNINITIALIZED))
1370 td->debugfs_dir = root;
1372 debugfs_create_file_unsafe("enable", 0644, root, td,
1374 debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops);
1375 debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops);
1376 debugfs_create_file("registers", 0444, root, td, &attr_registers_fops);
1380 static void inline dfll_debug_init(struct tegra_dfll *td) { }
1389 * @td: DFLL instance
1395 static void dfll_set_default_params(struct tegra_dfll *td)
1399 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32);
1401 dfll_writel(td, val, DFLL_CONFIG);
1403 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) |
1404 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) |
1405 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) |
1406 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) |
1407 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0);
1408 dfll_writel(td, val, DFLL_PARAMS);
1410 dfll_tune_low(td);
1411 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL);
1412 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL);
1417 * @td: DFLL instance
1423 static int dfll_init_clks(struct tegra_dfll *td)
1425 td->ref_clk = devm_clk_get(td->dev, "ref");
1426 if (IS_ERR(td->ref_clk)) {
1427 dev_err(td->dev, "missing ref clock\n");
1428 return PTR_ERR(td->ref_clk);
1431 td->soc_clk = devm_clk_get(td->dev, "soc");
1432 if (IS_ERR(td->soc_clk)) {
1433 dev_err(td->dev, "missing soc clock\n");
1434 return PTR_ERR(td->soc_clk);
1437 td->i2c_clk = devm_clk_get(td->dev, "i2c");
1438 if (IS_ERR(td->i2c_clk)) {
1439 dev_err(td->dev, "missing i2c clock\n");
1440 return PTR_ERR(td->i2c_clk);
1442 td->i2c_clk_rate = clk_get_rate(td->i2c_clk);
1449 * @td: DFLL instance
1456 static int dfll_init(struct tegra_dfll *td)
1460 td->ref_rate = clk_get_rate(td->ref_clk);
1461 if (td->ref_rate != REF_CLOCK_RATE) {
1462 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",
1463 td->ref_rate, REF_CLOCK_RATE);
1467 reset_control_deassert(td->dvco_rst);
1469 ret = clk_prepare(td->ref_clk);
1471 dev_err(td->dev, "failed to prepare ref_clk\n");
1475 ret = clk_prepare(td->soc_clk);
1477 dev_err(td->dev, "failed to prepare soc_clk\n");
1481 ret = clk_prepare(td->i2c_clk);
1483 dev_err(td->dev, "failed to prepare i2c_clk\n");
1487 td->last_unrounded_rate = 0;
1489 pm_runtime_enable(td->dev);
1490 pm_runtime_get_sync(td->dev);
1492 dfll_set_mode(td, DFLL_DISABLED);
1493 dfll_set_default_params(td);
1495 if (td->soc->init_clock_trimmers)
1496 td->soc->init_clock_trimmers();
1498 dfll_set_open_loop_config(td);
1500 dfll_init_out_if(td);
1502 pm_runtime_put_sync(td->dev);
1507 clk_unprepare(td->soc_clk);
1509 clk_unprepare(td->ref_clk);
1511 reset_control_assert(td->dvco_rst);
1525 struct tegra_dfll *td = dev_get_drvdata(dev);
1527 if (dfll_is_running(td)) {
1528 dev_err(td->dev, "DFLL still enabled while suspending\n");
1532 reset_control_assert(td->dvco_rst);
1549 struct tegra_dfll *td = dev_get_drvdata(dev);
1551 reset_control_deassert(td->dvco_rst);
1553 pm_runtime_get_sync(td->dev);
1555 dfll_set_mode(td, DFLL_DISABLED);
1556 dfll_set_default_params(td);
1558 if (td->soc->init_clock_trimmers)
1559 td->soc->init_clock_trimmers();
1561 dfll_set_open_loop_config(td);
1563 dfll_init_out_if(td);
1565 pm_runtime_put_sync(td->dev);
1579 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
1583 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
1586 align_step = uV / td->soc->alignment.step_uv;
1587 n_voltages = regulator_count_voltages(td->vdd_reg);
1589 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1593 reg_volt_id = reg_uV / td->soc->alignment.step_uv;
1599 dev_err(td->dev, "no voltage map entry for %d uV\n", uV);
1607 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
1611 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
1614 align_step = uV / td->soc->alignment.step_uv;
1615 n_voltages = regulator_count_voltages(td->vdd_reg);
1617 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1621 reg_volt_id = reg_uV / td->soc->alignment.step_uv;
1627 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV);
1633 * @td: DFLL instance
1640 static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
1645 int v_min = td->soc->cvb->min_millivolts * 1000;
1648 reg_volt = td->lut_uv[i];
1655 td->lut[i] = i;
1661 td->lut_size = i;
1663 (lut_bottom + 1 >= td->lut_size)) {
1664 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n",
1665 td->soc->cvb->min_millivolts);
1668 td->lut_bottom = lut_bottom;
1671 rate = get_dvco_rate_below(td, td->lut_bottom);
1673 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n",
1674 td->soc->cvb->min_millivolts);
1677 td->dvco_rate_min = rate;
1684 * @td: DFLL instance
1690 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC
1693 * On success, fills in td->lut and returns 0, or -err on failure.
1695 static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
1701 v = td->soc->cvb->min_millivolts * 1000;
1702 lut = find_vdd_map_entry_exact(td, v);
1705 td->lut[0] = lut;
1706 td->lut_bottom = 0;
1711 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
1716 if (v_opp <= td->soc->cvb->min_millivolts * 1000)
1717 td->dvco_rate_min = dev_pm_opp_get_freq(opp);
1726 selector = find_vdd_map_entry_min(td, v);
1729 if (selector != td->lut[j - 1])
1730 td->lut[j++] = selector;
1734 selector = find_vdd_map_entry_exact(td, v);
1737 if (selector != td->lut[j - 1])
1738 td->lut[j++] = selector;
1743 td->lut_size = j;
1745 if (!td->dvco_rate_min)
1746 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
1747 td->soc->cvb->min_millivolts);
1750 for (j = 0; j < td->lut_size; j++)
1751 td->lut_uv[j] =
1752 regulator_list_voltage(td->vdd_reg,
1753 td->lut[j]);
1760 static int dfll_build_lut(struct tegra_dfll *td)
1766 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
1768 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
1774 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1775 return dfll_build_pwm_lut(td, v_max);
1777 return dfll_build_i2c_lut(td, v_max);
1782 * @td: DFLL instance
1790 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest)
1792 int err = of_property_read_u32(td->dev->of_node, param, dest);
1795 dev_err(td->dev, "failed to read DT parameter %s: %d\n",
1805 * @td: DFLL instance
1811 static int dfll_fetch_i2c_params(struct tegra_dfll *td)
1819 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate))
1822 regmap = regulator_get_regmap(td->vdd_reg);
1826 td->i2c_slave_addr = i2c_client->addr;
1828 ret = regulator_get_hardware_vsel_register(td->vdd_reg,
1832 dev_err(td->dev,
1836 td->i2c_reg = vsel_reg;
1841 static int dfll_fetch_pwm_params(struct tegra_dfll *td)
1846 if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) {
1847 dev_err(td->dev,
1852 td->lut_uv[i] = td->soc->alignment.offset_uv +
1853 i * td->soc->alignment.step_uv;
1855 ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts",
1856 &td->reg_init_uV);
1858 dev_err(td->dev, "couldn't get initialized voltage\n");
1862 ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
1864 dev_err(td->dev, "couldn't get PWM period\n");
1867 td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);
1869 td->pwm_pin = devm_pinctrl_get(td->dev);
1870 if (IS_ERR(td->pwm_pin)) {
1871 dev_err(td->dev, "DT: missing pinctrl device\n");
1872 return PTR_ERR(td->pwm_pin);
1875 td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin,
1877 if (IS_ERR(td->pwm_enable_state)) {
1878 dev_err(td->dev, "DT: missing pwm enabled state\n");
1879 return PTR_ERR(td->pwm_enable_state);
1882 td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin,
1884 if (IS_ERR(td->pwm_disable_state)) {
1885 dev_err(td->dev, "DT: missing pwm disabled state\n");
1886 return PTR_ERR(td->pwm_disable_state);
1894 * @td: DFLL instance
1899 static int dfll_fetch_common_params(struct tegra_dfll *td)
1903 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl);
1904 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate);
1905 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode);
1906 ok &= read_dt_param(td, "nvidia,cf", &td->cf);
1907 ok &= read_dt_param(td, "nvidia,ci", &td->ci);
1908 ok &= read_dt_param(td, "nvidia,cg", &td->cg);
1909 td->cg_scale = of_property_read_bool(td->dev->of_node,
1912 if (of_property_read_string(td->dev->of_node, "clock-output-names",
1913 &td->output_clock_name)) {
1914 dev_err(td->dev, "missing clock-output-names property\n");
1938 struct tegra_dfll *td;
1946 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL);
1947 if (!td)
1949 td->dev = &pdev->dev;
1950 platform_set_drvdata(pdev, td);
1952 td->soc = soc;
1954 td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
1955 if (IS_ERR(td->dvco_rst)) {
1956 dev_err(td->dev, "couldn't get dvco reset\n");
1957 return PTR_ERR(td->dvco_rst);
1960 ret = dfll_fetch_common_params(td);
1962 dev_err(td->dev, "couldn't parse device tree parameters\n");
1966 if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) {
1967 td->pmu_if = TEGRA_DFLL_PMU_PWM;
1968 ret = dfll_fetch_pwm_params(td);
1970 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");
1971 if (IS_ERR(td->vdd_reg)) {
1972 dev_err(td->dev, "couldn't get vdd_cpu regulator\n");
1973 return PTR_ERR(td->vdd_reg);
1975 td->pmu_if = TEGRA_DFLL_PMU_I2C;
1976 ret = dfll_fetch_i2c_params(td);
1981 ret = dfll_build_lut(td);
1983 dev_err(td->dev, "couldn't build LUT\n");
1989 dev_err(td->dev, "no control register resource\n");
1993 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem));
1994 if (!td->base) {
1995 dev_err(td->dev, "couldn't ioremap DFLL control registers\n");
2001 dev_err(td->dev, "no i2c_base resource\n");
2005 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
2006 if (!td->i2c_base) {
2007 dev_err(td->dev, "couldn't ioremap i2c_base resource\n");
2013 dev_err(td->dev, "no i2c_controller_base resource\n");
2017 td->i2c_controller_base = devm_ioremap(td->dev, mem->start,
2019 if (!td->i2c_controller_base) {
2020 dev_err(td->dev,
2027 dev_err(td->dev, "no lut_base resource\n");
2031 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
2032 if (!td->lut_base) {
2033 dev_err(td->dev,
2038 ret = dfll_init_clks(td);
2045 ret = dfll_init(td);
2049 ret = dfll_register_clk(td);
2055 dfll_debug_init(td);
2071 struct tegra_dfll *td = platform_get_drvdata(pdev);
2074 if (td->mode != DFLL_DISABLED) {
2080 debugfs_remove_recursive(td->debugfs_dir);
2082 dfll_unregister_clk(td);
2085 clk_unprepare(td->ref_clk);
2086 clk_unprepare(td->soc_clk);
2087 clk_unprepare(td->i2c_clk);
2089 reset_control_assert(td->dvco_rst);
2091 return td->soc;