Lines Matching defs:rate
17 * complex when the target CPU speed is above a particular rate. The
60 /* DFLL_CONFIG: DFLL sample rate control */
191 * integrates the DVCO counter over - used for debug rate monitoring and
197 * REF_CLOCK_RATE: the DFLL reference clock rate currently supported by this
202 #define DVCO_RATE_TO_MULT(rate, ref_rate) ((rate) / ((ref_rate) / 2))
211 * the requested rate
245 * struct dfll_rate_req - target DFLL rate request data
246 * @rate: target frequency, after the postscaling
253 unsigned long rate;
466 * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate
468 * @dvco_rate: the DVCO rate
471 * the DVCO rate.
500 * DVCO rate control
506 unsigned long rate, prev_rate;
510 for (rate = 0, prev_rate = 0; ; rate++) {
511 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
521 prev_rate = rate;
782 * Set/get the DFLL's targeted output clock rate
786 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
788 * @rate: clock rate
791 * produces the given DFLL clock rate. This is used when forcing a value
792 * to the integrator during rate changes. Returns -ENOENT if a suitable
795 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
800 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
816 * dfll_calculate_rate_request - calculate DFLL parameters for a given rate
818 * @req: DFLL-rate-request structure
819 * @rate: the desired DFLL rate
821 * Populate the DFLL-rate-request record @req fields with the scale_bits
822 * and mult_bits fields, based on the target input rate. Returns 0 upon
823 * success, or -EINVAL if the requested rate in req->rate is too high
828 unsigned long rate)
833 * If requested rate is below the minimum DVCO rate, active the scaler.
835 * chip temperature and the actual minimum rate should be calibrated
839 if (rate < td->dvco_rate_min) {
842 scale = DIV_ROUND_CLOSEST(rate / 1000 * DFLL_FREQ_REQ_SCALE_MAX,
846 __func__, rate);
850 rate = td->dvco_rate_min;
853 /* Convert requested rate into frequency request and scale settings */
854 val = DVCO_RATE_TO_MULT(rate, td->ref_rate);
857 __func__, rate);
862 req->rate = dfll_scale_dvco_rate(req->scale_bits,
874 * @req: rate request structure
900 * tegra_dfll_request_rate - set the next rate for the DFLL to tune to
902 * @rate: clock rate to target
904 * Convert the requested clock rate @rate into the DFLL control logic
906 * adjust DFLL output rate accordingly. Otherwise, just save them
909 * if @rate is outside the DFLL's tunable range.
911 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate)
917 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",
922 ret = dfll_calculate_rate_request(td, &req, rate);
926 td->last_unrounded_rate = rate;
987 * forcing is disabled, and disables the output clock rate scaler.
1012 * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the
1024 if (req->rate == 0) {
1025 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",
1082 * mode when the clk is enabled. This requires that a DFLL rate request
1136 ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
1141 * Don't set the rounded rate, since it doesn't really matter as
1142 * the output rate will be voltage controlled anyway, and cpufreq
1149 static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1154 return dfll_request_rate(td, rate);
1228 * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
1230 * @ref_rate: DFLL reference clock rate
1242 * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
1245 * If the DFLL is enabled, return the last rate reported by the DFLL's
1252 * measured rate from when the DFLL was active.
1375 debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops);
1462 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",
1643 unsigned long rate, reg_volt;
1670 /* determine rate boundaries */
1671 rate = get_dvco_rate_below(td, td->lut_bottom);
1672 if (!rate) {
1677 td->dvco_rate_min = rate;
1697 unsigned long rate, v, v_opp;
1708 for (j = 1, rate = 0; ; rate++) {
1711 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
1762 unsigned long rate, v_max;
1765 rate = ULONG_MAX;
1766 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
1819 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate))
1904 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate);