Lines Matching defs:node
556 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
561 reg = of_iomap(node, 0);
564 node);
568 return sunxi_factors_register(node, data, &clk_lock, reg);
571 static void __init sun4i_pll1_clk_setup(struct device_node *node)
573 sunxi_factors_clk_setup(node, &sun4i_pll1_data);
578 static void __init sun6i_pll1_clk_setup(struct device_node *node)
580 sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);
585 static void __init sun8i_pll1_clk_setup(struct device_node *node)
587 sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);
592 static void __init sun7i_pll4_clk_setup(struct device_node *node)
594 sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);
599 static void __init sun5i_ahb_clk_setup(struct device_node *node)
601 sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);
606 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
608 sunxi_factors_clk_setup(node, &sun6i_ahb1_data);
613 static void __init sun4i_apb1_clk_setup(struct device_node *node)
615 sunxi_factors_clk_setup(node, &sun4i_apb1_data);
620 static void __init sun7i_out_clk_setup(struct device_node *node)
622 sunxi_factors_clk_setup(node, &sun7i_a20_out_data);
650 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
655 const char *clk_name = node->name;
660 reg = of_iomap(node, 0);
662 pr_err("Could not map registers for mux-clk: %pOF\n", node);
666 i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
667 if (of_property_read_string(node, "clock-output-names", &clk_name)) {
669 __func__, node);
684 if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
697 static void __init sun4i_cpu_clk_setup(struct device_node *node)
700 sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL);
705 static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
707 sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0);
712 static void __init sun8i_ahb2_clk_setup(struct device_node *node)
714 sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0);
775 static void __init sunxi_divider_clk_setup(struct device_node *node,
779 const char *clk_name = node->name;
783 reg = of_iomap(node, 0);
785 pr_err("Could not map registers for mux-clk: %pOF\n", node);
789 clk_parent = of_clk_get_parent_name(node, 0);
791 if (of_property_read_string(node, "clock-output-names", &clk_name)) {
793 __func__, node);
807 if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
814 of_clk_del_provider(node);
826 static void __init sun4i_ahb_clk_setup(struct device_node *node)
828 sunxi_divider_clk_setup(node, &sun4i_ahb_data);
833 static void __init sun4i_apb0_clk_setup(struct device_node *node)
835 sunxi_divider_clk_setup(node, &sun4i_apb0_data);
840 static void __init sun4i_axi_clk_setup(struct device_node *node)
842 sunxi_divider_clk_setup(node, &sun4i_axi_data);
847 static void __init sun8i_axi_clk_setup(struct device_node *node)
849 sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);
943 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
968 of_property_read_string_index(node, "clock-output-names",
977 of_property_read_string_index(node, "clock-output-names",
992 pclk = sunxi_factors_clk_setup(node, &factors);
999 reg = of_iomap(node, 0);
1001 pr_err("Could not map registers for divs-clk: %pOF\n", node);
1020 if (of_property_read_string_index(node, "clock-output-names",
1092 if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) {
1110 static void __init sun4i_pll5_clk_setup(struct device_node *node)
1112 sunxi_divs_clk_setup(node, &pll5_divs_data);
1117 static void __init sun4i_pll6_clk_setup(struct device_node *node)
1119 sunxi_divs_clk_setup(node, &pll6_divs_data);
1124 static void __init sun6i_pll6_clk_setup(struct device_node *node)
1126 sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data);
1162 static void __init sun6i_display_setup(struct device_node *node)
1164 sunxi_factors_clk_setup(node, &sun6i_display_data);