Lines Matching refs:parent
62 /* apply pre-divider first if parent is pll4 */
73 u8 parent, unsigned long parent_rate)
79 * frequencies higher than the parent frequency
86 /* calculate pre-divider if parent is pll4 */
87 if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) {
116 struct clk_hw *parent, *best_parent = NULL;
121 /* find the parent that can help provide the fastest rate <= rate */
124 parent = clk_hw_get_parent_by_index(clk, i);
125 if (!parent)
128 parent_rate = clk_hw_round_rate(parent, rate);
130 parent_rate = clk_hw_get_rate(parent);
136 best_parent = parent;
157 u8 div, pre_div, parent;
164 /* need to know which parent is used to apply pre-divider */
165 parent = SUN9I_CPUS_MUX_GET_PARENT(reg);
166 sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate);