Lines Matching defs:reg
19 return !(readl(common->base + common->reg) & cf->enable);
26 u32 reg;
32 reg = readl(common->base + common->reg);
33 writel(reg & ~cf->enable, common->base + common->reg);
41 u32 reg;
47 reg = readl(common->base + common->reg);
48 writel(reg | cf->enable, common->base + common->reg);
65 u32 reg;
75 reg = readl(common->base + common->reg);
77 pr_debug("%s: clock reg is 0x%x (select is 0x%x)\n",
78 clk_hw_get_name(&common->hw), reg, cf->select);
80 return (reg & cf->select) ? cf->rates[1] : cf->rates[0];
88 u32 reg, sel;
101 reg = readl(common->base + common->reg);
102 reg &= ~cf->select;
103 writel(reg | sel, common->base + common->reg);