Lines Matching defs:output
253 static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
267 if (output < 800000000 || output > 1600000000)
271 output /= 1000;
274 n = i * output / (2 * input);
284 new_deviation = abs(new_freq - output);
400 /* PLL output structure
401 * FVCO >> /2 >> FVCOBY2 (no output)
404 * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
409 * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
414 static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
423 if (output < 19000000 || output > 3000000000u)
433 n = output / (infin * 2);
441 if (new_freq < output)
444 new_deviation = new_freq - output;
734 if (of_property_read_string_index(np, "clock-output-names",