Lines Matching defs:input
20 * Maximum input clock to the PLL before we divide it down by 2
71 static int clk_fs660c32_dig_get_params(unsigned long input,
160 * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
205 * Use a fixed input clock noise bandwidth filter for the moment
260 static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
265 *rate = input * nd;
287 static int clk_fs660c32_vco_get_params(unsigned long input,
300 if (input > 40000000)
305 input /= 1000;
308 n = output * pdiv / input;
560 static int clk_fs660c32_dig_get_rate(unsigned long input,
578 *rate = (unsigned long)div64_u64(input * P20 * 32, res);
585 signed long input, unsigned long output, uint64_t *p,
594 *p = (uint64_t)input * P20 - (32LL + (uint64_t)m) * val * (P20 / 32LL);
606 clk_fs660c32_dig_get_rate(input, &fs_tmp, &new_freq);
620 static int clk_fs660c32_dig_get_params(unsigned long input,
637 input, output, &p1, fs);
639 input, output, &p2, fs);
648 input, output, &p, fs);
669 clk_fs660c32_dig_get_rate(input, &fs_tmp, &new_freq);