Lines Matching refs:pll
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \
25 pll->factors[member].width
27 #define pmask(pll, member) \
28 ((pwidth(pll, member)) ? \
29 GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \
30 pshift(pll, member)) : 0)
32 #define pinternal(pll, cfg, member) \
33 (cfg[pindex(pll, member)] & pmask(pll, member))
35 #define pinternal_val(pll, cfg, member) \
36 (pinternal(pll, cfg, member) >> pshift(pll, member))
39 sprd_pll_read(const struct sprd_pll *pll, u8 index)
41 const struct sprd_clk_common *common = &pll->common;
44 if (WARN_ON(index >= pll->regs_num))
53 sprd_pll_write(const struct sprd_pll *pll, u8 index,
56 const struct sprd_clk_common *common = &pll->common;
60 if (WARN_ON(index >= pll->regs_num))
69 static unsigned long pll_get_refin(const struct sprd_pll *pll)
74 if (pwidth(pll, PLL_REFIN)) {
75 index = pindex(pll, PLL_REFIN);
76 shift = pshift(pll, PLL_REFIN);
77 mask = pmask(pll, PLL_REFIN);
78 refin_id = (sprd_pll_read(pll, index) & mask) >> shift;
98 static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
102 u32 i, mask, regs_num = pll->regs_num;
112 cfg[i] = sprd_pll_read(pll, i);
114 refin = pll_get_refin(pll);
116 if (pinternal(pll, cfg, PLL_PREDIV))
119 if (pwidth(pll, PLL_POSTDIV) &&
120 ((pll->fflag == 1 && pinternal(pll, cfg, PLL_POSTDIV)) ||
121 (!pll->fflag && !pinternal(pll, cfg, PLL_POSTDIV))))
124 if (!pinternal(pll, cfg, PLL_DIV_S)) {
125 rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M;
127 nint = pinternal_val(pll, cfg, PLL_NINT);
128 if (pinternal(pll, cfg, PLL_SDM_EN))
129 kint = pinternal_val(pll, cfg, PLL_KINT);
131 mask = pmask(pll, PLL_KINT);
133 k1 = pll->k1;
134 k2 = pll->k2;
144 #define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \
145 (((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT))
147 static int _sprd_pll_set_rate(const struct sprd_pll *pll,
154 u32 regs_num = pll->regs_num, i = 0;
162 refin = pll_get_refin(pll);
164 mask = pmask(pll, PLL_PREDIV);
165 index = pindex(pll, PLL_PREDIV);
166 width = pwidth(pll, PLL_PREDIV);
167 if (width && (sprd_pll_read(pll, index) & mask))
170 mask = pmask(pll, PLL_POSTDIV);
171 index = pindex(pll, PLL_POSTDIV);
172 width = pwidth(pll, PLL_POSTDIV);
174 if (width && ((pll->fflag == 1 && fvco <= pll->fvco) ||
175 (pll->fflag == 0 && fvco > pll->fvco)))
178 if (width && fvco <= pll->fvco)
181 mask = pmask(pll, PLL_DIV_S);
182 index = pindex(pll, PLL_DIV_S);
186 mask = pmask(pll, PLL_SDM_EN);
187 index = pindex(pll, PLL_SDM_EN);
192 mask = pmask(pll, PLL_NINT);
193 index = pindex(pll, PLL_NINT);
194 shift = pshift(pll, PLL_NINT);
198 mask = pmask(pll, PLL_KINT);
199 index = pindex(pll, PLL_KINT);
200 width = pwidth(pll, PLL_KINT);
201 shift = pshift(pll, PLL_KINT);
208 ibias_val = pll_get_ibias(fvco, pll->itable);
210 mask = pmask(pll, PLL_IBIAS);
211 index = pindex(pll, PLL_IBIAS);
212 shift = pshift(pll, PLL_IBIAS);
218 sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val);
219 ret |= SPRD_PLL_WRITE_CHECK(pll, i, cfg[i].msk,
225 udelay(pll->udelay);
234 struct sprd_pll *pll = hw_to_sprd_pll(hw);
236 return _sprd_pll_recalc_rate(pll, parent_rate);
243 struct sprd_pll *pll = hw_to_sprd_pll(hw);
245 return _sprd_pll_set_rate(pll, rate, parent_rate);
250 struct sprd_pll *pll = hw_to_sprd_pll(hw);
252 udelay(pll->udelay);