Lines Matching refs:NULL
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
147 clk_register_clkdev(clk, NULL, "60000000.clcd");
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
151 clk_register_clkdev(clk, NULL, "94000000.flash");
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
155 clk_register_clkdev(clk, NULL, "70000000.sdhci");
157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
159 clk_register_clkdev(clk, NULL, "a9000000.gpio");
161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
163 clk_register_clkdev(clk, NULL, "a0000000.kbd");
175 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
177 clk_register_clkdev(clk, "emi", NULL);
179 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
181 clk_register_clkdev(clk, NULL, "44000000.flash");
183 clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
185 clk_register_clkdev(clk, NULL, "tdm");
187 clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
189 clk_register_clkdev(clk, NULL, "b2000000.serial");
191 clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
193 clk_register_clkdev(clk, NULL, "b2080000.serial");
195 clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
197 clk_register_clkdev(clk, NULL, "b2100000.serial");
199 clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
201 clk_register_clkdev(clk, NULL, "b2180000.serial");
203 clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
205 clk_register_clkdev(clk, NULL, "b2200000.serial");
253 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
255 clk_register_clkdev(clk, "smii_125m_pad", NULL);
257 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
259 clk_register_clkdev(clk, NULL, "90000000.clcd");
261 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
263 clk_register_clkdev(clk, "emi", NULL);
265 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
267 clk_register_clkdev(clk, NULL, "4c000000.flash");
269 clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
271 clk_register_clkdev(clk, NULL, "a7000000.i2c");
273 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
275 clk_register_clkdev(clk, NULL, "a8000000.pwm");
277 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
279 clk_register_clkdev(clk, NULL, "a5000000.spi");
281 clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
283 clk_register_clkdev(clk, NULL, "a6000000.spi");
285 clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
287 clk_register_clkdev(clk, NULL, "c_can_platform.0");
289 clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
291 clk_register_clkdev(clk, NULL, "c_can_platform.1");
293 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
295 clk_register_clkdev(clk, NULL, "a9400000.i2s");
297 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
302 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
304 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
307 clk_register_clkdev(clk, "i2s_sclk", NULL);
309 clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
313 clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
317 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
322 clk_register_clkdev(clk, NULL, "a9300000.serial");
324 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
329 clk_register_clkdev(clk, NULL, "70000000.sdhci");
331 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
335 clk_register_clkdev(clk, NULL, "smii_pclk");
337 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
338 clk_register_clkdev(clk, NULL, "smii");
340 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
345 clk_register_clkdev(clk, NULL, "a3000000.serial");
349 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
354 clk_register_clkdev(clk, NULL, "a4000000.serial");
358 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
363 clk_register_clkdev(clk, NULL, "a9100000.serial");
365 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
370 clk_register_clkdev(clk, NULL, "a9200000.serial");
372 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
377 clk_register_clkdev(clk, NULL, "60000000.serial");
379 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
384 clk_register_clkdev(clk, NULL, "60100000.serial");
394 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
395 clk_register_clkdev(clk, "osc_32k_clk", NULL);
397 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
398 clk_register_clkdev(clk, "osc_24m_clk", NULL);
401 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
403 clk_register_clkdev(clk, NULL, "fc900000.rtc");
406 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
408 clk_register_clkdev(clk, "pll3_clk", NULL);
410 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
412 clk_register_clkdev(clk, NULL, "fc880000.wdt");
414 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
416 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
417 clk_register_clkdev(clk, "vco1_clk", NULL);
418 clk_register_clkdev(clk1, "pll1_clk", NULL);
420 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
422 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
423 clk_register_clkdev(clk, "vco2_clk", NULL);
424 clk_register_clkdev(clk1, "pll2_clk", NULL);
427 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
429 clk_register_clkdev(clk, "cpu_clk", NULL);
431 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
434 clk_register_clkdev(clk, "ahb_clk", NULL);
437 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
439 clk_register_clkdev(clk, "uart_syn_clk", NULL);
440 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
442 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
447 clk_register_clkdev(clk, "uart0_mclk", NULL);
449 clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
452 clk_register_clkdev(clk, NULL, "d0000000.serial");
455 FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
457 clk_register_clkdev(clk, "firda_syn_clk", NULL);
458 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
460 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
465 clk_register_clkdev(clk, "firda_mclk", NULL);
467 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
470 clk_register_clkdev(clk, NULL, "firda");
475 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
479 clk_register_clkdev(clk, NULL, "gpt0");
483 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
487 clk_register_clkdev(clk, "gpt1_mclk", NULL);
488 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
491 clk_register_clkdev(clk, NULL, "gpt1");
495 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
499 clk_register_clkdev(clk, "gpt2_mclk", NULL);
500 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
503 clk_register_clkdev(clk, NULL, "gpt2");
507 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
509 clk_register_clkdev(clk, "gen0_syn_clk", NULL);
510 clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
513 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
515 clk_register_clkdev(clk, "gen1_syn_clk", NULL);
516 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
518 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
522 clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
525 "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
527 clk_register_clkdev(clk, "gen2_syn_clk", NULL);
528 clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
531 "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
533 clk_register_clkdev(clk, "gen3_syn_clk", NULL);
534 clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
537 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
539 clk_register_clkdev(clk, NULL, "e1800000.ehci");
540 clk_register_clkdev(clk, NULL, "e1900000.ohci");
541 clk_register_clkdev(clk, NULL, "e2100000.ohci");
543 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
545 clk_register_clkdev(clk, "usbh.0_clk", NULL);
547 clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
549 clk_register_clkdev(clk, "usbh.1_clk", NULL);
551 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
553 clk_register_clkdev(clk, NULL, "e1100000.usbd");
556 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
558 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
560 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
563 clk_register_clkdev(clk, "ddr_clk", NULL);
565 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
568 clk_register_clkdev(clk, "apb_clk", NULL);
570 clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
572 clk_register_clkdev(clk, "amem_clk", NULL);
574 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
576 clk_register_clkdev(clk, NULL, "c3_clk");
578 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
580 clk_register_clkdev(clk, NULL, "fc400000.dma");
582 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
584 clk_register_clkdev(clk, NULL, "e0800000.eth");
586 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
588 clk_register_clkdev(clk, NULL, "d0180000.i2c");
590 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
592 clk_register_clkdev(clk, NULL, "jpeg");
594 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
596 clk_register_clkdev(clk, NULL, "fc000000.flash");
599 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
601 clk_register_clkdev(clk, NULL, "d0080000.adc");
603 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
605 clk_register_clkdev(clk, NULL, "fc980000.gpio");
607 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
609 clk_register_clkdev(clk, NULL, "d0100000.spi");
612 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
614 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
616 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
618 clk_register_clkdev(clk, "ras_apb_clk", NULL);
621 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
623 clk_register_clkdev(clk, "ras_32k_clk", NULL);
625 clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
627 clk_register_clkdev(clk, "ras_24m_clk", NULL);
629 clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
631 clk_register_clkdev(clk, "ras_pll1_clk", NULL);
633 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
635 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
637 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
639 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
641 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
644 clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
646 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
649 clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
651 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
654 clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
656 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
659 clk_register_clkdev(clk, "ras_syn3_gclk", NULL);