Lines Matching defs:reg
42 unsigned long divf, divq, reg;
46 reg = readl(socfpgaclk->hw.reg);
51 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
52 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
63 pll_src = readl(socfpgaclk->hw.reg);
76 u32 reg;
86 of_property_read_u32(node, "reg", ®);
96 pll_clk->hw.reg = clk_mgr_base_addr + reg;