Lines Matching defs:reg
38 unsigned long divf, divq, reg;
41 /* read VCO1 reg for numerator and denominator */
42 reg = readl(socfpgaclk->hw.reg + 0x4);
43 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
44 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
55 pll_src = readl(socfpgaclk->hw.reg);
69 u32 reg;
79 of_property_read_u32(node, "reg", ®);
89 pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;