Lines Matching refs:clk_phase
117 u32 clk_phase[2];
119 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
127 switch (socfpgaclk->clk_phase[i]) {
129 clk_phase[i] = 0;
132 clk_phase[i] = 1;
135 clk_phase[i] = 2;
138 clk_phase[i] = 3;
141 clk_phase[i] = 4;
144 clk_phase[i] = 5;
147 clk_phase[i] = 6;
150 clk_phase[i] = 7;
153 clk_phase[i] = 0;
157 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
175 u32 clk_phase[2];
223 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
225 socfpga_clk->clk_phase[0] = clk_phase[0];
226 socfpga_clk->clk_phase[1] = clk_phase[1];