Lines Matching defs:clk_phase
43 u32 clk_phase[2];
45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
46 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
47 switch (socfpgaclk->clk_phase[i]) {
49 clk_phase[i] = 0;
52 clk_phase[i] = 1;
55 clk_phase[i] = 2;
58 clk_phase[i] = 3;
61 clk_phase[i] = 4;
64 clk_phase[i] = 5;
67 clk_phase[i] = 6;
70 clk_phase[i] = 7;
73 clk_phase[i] = 0;
78 hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
83 pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n",
99 u32 clk_phase[2];
139 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
141 socfpga_clk->clk_phase[0] = clk_phase[0];
142 socfpga_clk->clk_phase[1] = clk_phase[1];