Lines Matching refs:reg
59 static inline unsigned long clkc_readl(unsigned reg)
61 return readl(sirfsoc_clk_vbase + reg);
64 static inline void clkc_writel(u32 val, unsigned reg)
66 writel(val, sirfsoc_clk_vbase + reg);
130 unsigned long fin, nf, nr, od, reg;
149 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
150 clkc_writel(reg, clk->regofs);
152 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
153 clkc_writel((nf >> 1) - 1, reg);
155 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
156 while (!(clkc_readl(reg) & BIT(6)))
244 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
245 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
246 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
256 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
257 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
258 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
263 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
264 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
380 unsigned ratio, wait, hold, reg;
395 reg = clkc_readl(clk->regofs);
396 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
397 reg |= (wait << 16) | (hold << 20) | BIT(25);
398 clkc_writel(reg, clk->regofs);
637 u32 reg;
642 reg = clk->enable_bit / 32;
643 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
645 return !!(clkc_readl(reg) & BIT(bit));
650 u32 val, reg;
657 reg = clk->enable_bit / 32;
658 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
660 val = clkc_readl(reg) | BIT(bit);
661 clkc_writel(val, reg);
667 u32 val, reg;
674 reg = clk->enable_bit / 32;
675 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
677 val = clkc_readl(reg) & ~BIT(bit);
678 clkc_writel(val, reg);