Lines Matching refs:list
95 /* register a list of aliases */
97 const struct samsung_clock_alias *list,
103 for (idx = 0; idx < nr_clk; idx++, list++) {
104 if (!list->id) {
110 clk_hw = ctx->clk_data.hws[list->id];
113 list->id);
117 ret = clk_hw_register_clkdev(clk_hw, list->alias,
118 list->dev_name);
121 __func__, list->alias);
125 /* register a list of fixed clocks */
127 const struct samsung_fixed_rate_clock *list,
133 for (idx = 0; idx < nr_clk; idx++, list++) {
134 clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name,
135 list->parent_name, list->flags, list->fixed_rate);
138 list->name);
142 samsung_clk_add_lookup(ctx, clk_hw, list->id);
148 ret = clk_hw_register_clkdev(clk_hw, list->name, NULL);
151 __func__, list->name);
155 /* register a list of fixed factor clocks */
157 const struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
162 for (idx = 0; idx < nr_clk; idx++, list++) {
163 clk_hw = clk_hw_register_fixed_factor(ctx->dev, list->name,
164 list->parent_name, list->flags, list->mult, list->div);
167 list->name);
171 samsung_clk_add_lookup(ctx, clk_hw, list->id);
175 /* register a list of mux clocks */
177 const struct samsung_mux_clock *list,
183 for (idx = 0; idx < nr_clk; idx++, list++) {
184 clk_hw = clk_hw_register_mux(ctx->dev, list->name,
185 list->parent_names, list->num_parents, list->flags,
186 ctx->reg_base + list->offset,
187 list->shift, list->width, list->mux_flags, &ctx->lock);
190 list->name);
194 samsung_clk_add_lookup(ctx, clk_hw, list->id);
198 /* register a list of div clocks */
200 const struct samsung_div_clock *list,
206 for (idx = 0; idx < nr_clk; idx++, list++) {
207 if (list->table)
209 list->name, list->parent_name, list->flags,
210 ctx->reg_base + list->offset,
211 list->shift, list->width, list->div_flags,
212 list->table, &ctx->lock);
214 clk_hw = clk_hw_register_divider(ctx->dev, list->name,
215 list->parent_name, list->flags,
216 ctx->reg_base + list->offset, list->shift,
217 list->width, list->div_flags, &ctx->lock);
220 list->name);
224 samsung_clk_add_lookup(ctx, clk_hw, list->id);
228 /* register a list of gate clocks */
230 const struct samsung_gate_clock *list,
236 for (idx = 0; idx < nr_clk; idx++, list++) {
237 clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
238 list->flags, ctx->reg_base + list->offset,
239 list->bit_idx, list->gate_flags, &ctx->lock);
242 list->name);
246 samsung_clk_add_lookup(ctx, clk_hw, list->id);
343 * for each CMU. It also add CMU register list to register cache.