clk-pll.c - OpenGrok cross reference for /kernel/linux/linux-5.10/drivers/clk/samsung/clk-pll.c

Lines Matching refs:pll_con0
286 	u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
290 	pll_con0 = readl_relaxed(pll->con_reg);
292 	mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
293 	pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
294 	sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
305 	const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
309 	old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
310 	old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
321 	u32 tmp, pll_con0, pll_con1;
331 	pll_con0 = readl_relaxed(pll->con_reg);
334 	if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
336 		pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
337 		pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
338 		writel_relaxed(pll_con0, pll->con_reg);
347 	pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
350 	pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
353 	writel_relaxed(pll_con0, pll->con_reg);
360 	if (pll_con0 & BIT(pll->enable_offs)) {
421 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
426 	old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
427 	old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
551 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
554 	pll_con0 = readl_relaxed(pll->con_reg);
556 	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
558 	pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
559 	sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
572 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
577 	old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
578 	old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
734 	u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
737 	pll_con0 = readl_relaxed(pll->con_reg);
739 	mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
740 	pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
741 	sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
1082 	u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
1085 	pll_con0 = readl_relaxed(pll->con_reg);
1086 	mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK;
1087 	pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK;
1088 	sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK;
1177 	u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
1181 	pll_con0 = readl_relaxed(pll->con_reg);
1183 	mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
1184 	pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
1185 	sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
1199 	u32 tmp, pll_con0, pll_con2;
1209 	pll_con0 = readl_relaxed(pll->con_reg);
1213 	pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
1216 	pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
1217 	pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
1218 	pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
1219 	pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
1220 	pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
1229 	writel_relaxed(pll_con0, pll->con_reg);