Lines Matching defs:con0
439 u32 con0, con1;
450 con0 = readl_relaxed(pll->con_reg);
453 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
455 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
456 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
457 writel_relaxed(con0, pll->con_reg);
463 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
466 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
489 writel_relaxed(con0, pll->con_reg);
590 u32 con0, con1, lock;
601 con0 = readl_relaxed(pll->con_reg);
604 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
606 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
607 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
608 writel_relaxed(con0, pll->con_reg);
621 con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
625 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
629 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
632 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
647 writel_relaxed(con0, pll->con_reg);
1105 u32 con0, con1;
1115 con0 = readl_relaxed(pll->con_reg);
1122 con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
1125 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
1128 con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
1129 writel_relaxed(con0, pll->con_reg);
1137 con0 = readl_relaxed(pll->con_reg);
1138 } while (!(con0 & (PLL2650X_LOCK_STAT_MASK