Lines Matching refs:ctx
1036 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1059 samsung_clk_register_fixed_rate(ctx, &fclk, 1);
1235 struct samsung_clk_provider *ctx;
1244 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1245 hws = ctx->clk_data.hws;
1247 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
1251 exynos4_clk_register_finpll(ctx);
1254 samsung_clk_register_mux(ctx, exynos4210_mux_early,
1268 samsung_clk_register_pll(ctx, exynos4210_plls,
1280 samsung_clk_register_pll(ctx, exynos4x12_plls,
1284 samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1286 samsung_clk_register_mux(ctx, exynos4_mux_clks,
1288 samsung_clk_register_div(ctx, exynos4_div_clks,
1290 samsung_clk_register_gate(ctx, exynos4_gate_clks,
1292 samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1296 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1298 samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1300 samsung_clk_register_div(ctx, exynos4210_div_clks,
1302 samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1304 samsung_clk_register_fixed_factor(ctx,
1307 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1312 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1314 samsung_clk_register_div(ctx, exynos4x12_div_clks,
1316 samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1318 samsung_clk_register_fixed_factor(ctx,
1322 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1342 samsung_clk_of_add_provider(np, ctx);